Buried-Gate Memory Structure With Strained Stressors for Short-Channel Control
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Solution Overview
Problem
As semiconductor devices are scaled down, they can experience short channel effects and reduced carrier mobility, leading to performance issues and increased energy consumption.
Innovation Solution
A semiconductor memory structure with a buried gate and strained drain and source stressors is developed, where the gate is completely buried under the substrate to prevent short channel effects, and the strained stressors increase interatomic distance in the silicon layer, enhancing carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the channel length is scaled down to reduce device size, then device capacity and integration density are improved, but short channel effects occur leading to degraded device performance
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional buried gate structure that extends vertically into the substrate. This dimensional change allows the gate to maintain effective control over the channel despite reduced horizontal dimensions, thereby preventing short channel effects while enabling further device scaling
Solution Approach 2:
The buried gate structure is formed beforehand in the substrate before the channel formation is completed. This preliminary positioning of the gate ensures proper electric field distribution and channel control from the outset, preventing short channel effects before they can manifest during device operation
2Ease of manufacture
If conventional silicon material is used in the channel, then manufacturing simplicity is maintained, but carrier mobility is reduced leading to higher energy consumption
Solution Approach 1:
The patent changes the physical parameters of the silicon material by introducing mechanical strain through the buried gate structure. This strain modifies the crystal lattice spacing and electronic band structure, thereby enhancing carrier mobility without requiring a complete material substitution, thus maintaining manufacturing compatibility while reducing energy consumption
Solution Approach 2:
The patent creates a composite structure where strained silicon forms the channel and the buried gate material (such as silicon germanium or other semiconductors) provides the strain. This composite arrangement combines the electrical properties of silicon with the structural properties of the gate material to achieve enhanced carrier mobility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces short channel effects, improves carrier mobility, and results in semiconductor devices with better performance, lower energy consumption, and higher reliability.
Implementation Method 1
Strained silicon is a layer of silicon in which the silicon atoms are stretched beyond their normal interatomic distance. Moving these silicon atoms farther apart reduces the atomic forces that interfere with the movement of electrons through the transistors and thus improves carrier mobility
Data Source
AI summary
The present disclosure provides a semiconductor memory structure. The semiconductor memory structure includes a substrate, a gate structure, a drain stressor and a source stressor. The gate structure is disposed in the substrate. Each of the source stressor and the drain stressor includes a strained part disposed in the substrate.