Buried Gate Memory Transistors for DRAM Reliability
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Solution Overview
Problem
The reduction in size of transistors in DRAMs leads to increased channel resistance and disturb errors due to the proximity of memory cells, causing reliability issues and data corruption during ON/OFF operations.
Innovation Solution
The semiconductor device design includes a configuration with buried gate trenches and specific impurity diffusion layers to ensure sufficient ON current and prevent interference between adjacent transistors, featuring a channel structure that reduces channel resistance and minimizes electron transfer between adjacent transistors, thereby preventing disturb errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistor size is reduced to increase memory cell density, then memory cell size is reduced, but channel resistance increases and threshold voltage decreases causing performance deterioration
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional FinFET structures. By forming vertical fins in the semiconductor substrate, the channel extends in the vertical dimension, increasing the effective channel length and surface area for charge carrier flow. This dimensional change allows maintaining low channel resistance even as the planar footprint is reduced, thus improving transistor performance in scaled memory cells.
Solution Approach 2:
The gate electrode is segmented into multiple sections along the channel length, with different potential levels applied to each segment. This segmentation allows independent control of different channel regions, enabling optimization of charge carrier flow and threshold voltage control. The segmented gate structure helps maintain effective channel control and performance in reduced-size transistors by addressing different portions of the channel with tailored electrical conditions.
2Productivity
If transistor size is reduced, then memory cell density increases, but short channel effect becomes more prominent causing sub-threshold current increase
Solution Approach 1:
By forming vertical fins that extend into the substrate, the channel length is effectively increased in the vertical dimension while the planar dimensions are reduced. This three-dimensional channel structure provides better electrostatic control over the channel, suppressing short channel effects and reducing sub-threshold current leakage even at high memory cell densities.
Solution Approach 2:
The patent employs a composite structure combining semiconductor material fins with insulating materials (such as silicon oxide or silicon nitride) in the gate dielectric and surrounding regions. This composite material approach enhances the electrostatic control of the gate over the channel, improving suppression of short channel effects and reducing unwanted current leakage while maintaining high device density.
3Area of moving object
If memory cells are positioned closer together, then area efficiency improves, but interference between adjacent transistors increases causing disturb errors
Solution Approach 1:
By stacking memory cells vertically using FinFET structures and multiple gate segments, the patent achieves high area efficiency in the vertical dimension while maintaining adequate spacing in the planar dimension. This vertical stacking allows dense packing without increasing planar interference between adjacent transistors, as each cell occupies a small footprint but extends vertically with isolated channels.
Solution Approach 2:
The gate electrode is divided into multiple independently controllable segments. This segmentation enables selective activation of specific transistor regions and allows for reduced voltage levels or disabled states in adjacent cells during read/write operations. By controlling gate segments independently, the patent minimizes electrical interference and disturb errors between closely spaced memory cells while maintaining high area efficiency.
Data Source
AI summary
A device includes a semiconductor region surrounded with the isolation region and includes a first active region, a channel region and a second active region arranged in that order in a first direction. A first side portion of the first active region and a second side portion of the second active region faces each other across a top surface of the channel region in the first direction. A gate electrode covers the top surface and the first and second side portions and extends in a second direction that intersects the first direction. A first diffusion layer is formed in the first active region. A second diffusion layer is formed in the second active region. An embedded contact plug is formed in the first active region and extends downwardly from the upper surface of the semiconductor region and contacts with the first diffusion layer.