Buried-Gate MOS Transistor Stress Engineering
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Solution Overview
Problem
Conventional buried-gate MOS transistors do not effectively optimize electron mobility in the channel area or contact resistance, limiting current drive performance.
Innovation Solution
Applying tensile stress in the channel length direction and compressive stress in the channel width direction to the channel area, with a gate electrode and cap portion having compressive stress, and using a semiconductor substrate with specific crystal orientations to enhance electron mobility and current driving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional buried-gate MOS transistor structure is used, then contact area on active area is maximized, but electron mobility in channel area is not optimized
Solution Approach 1:
The patent applies different stress conditions to different regions of the channel area. Specifically, tensile stress is applied in the channel length direction and compressive stress is applied in the channel width direction, creating localized stress fields that optimize electron mobility in the channel region without affecting the contact area geometry. This local quality modification resolves the contradiction by improving electron mobility through targeted stress application while maintaining the maximized contact area of the conventional structure.
Solution Approach 2:
The patent changes the physical parameters of the channel area by applying controlled mechanical stress. The stress state is modified by introducing tensile stress along the channel length direction and compressive stress along the channel width direction, which alters the band structure and carrier mobility characteristics. This parameter change approach enables optimization of electron mobility while preserving the conventional structure's contact area advantages.
2Device complexity
If conventional buried-gate MOS transistor structure is used, then device simplicity is maintained, but current drive performance is not enhanced
Solution Approach 1:
The patent enhances current drive performance by changing the stress parameters in the channel area without modifying the fundamental device structure. By applying tensile stress in the channel length direction and compressive stress in the channel width direction, the carrier mobility is improved, leading to enhanced current drive performance while maintaining the simplicity of the conventional buried-gate structure.
Solution Approach 2:
The patent effectively creates a composite stress state in the channel area by combining tensile and compressive stress fields. This composite stress configuration optimizes electron mobility through the interplay of different stress components, enhancing current drive performance while keeping the structural design simple and conventional.
3Reliability
If stress is applied to channel area, then electron mobility is enhanced, but device structure complexity increases
Solution Approach 1:
The patent employs self-service mechanisms where the device structure itself generates the required stress fields. By designing the device geometry and material composition appropriately, the structure automatically creates tensile stress in the channel length direction and compressive stress in the channel width direction without requiring external stress application equipment or complex additional components. This self-service approach enhances electron mobility while minimizing the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances electron mobility and current driving performance by optimizing stress distribution within the buried-gate MOS transistor, as demonstrated by simulation results showing increased tensile stress in the channel area.
Implementation Method 1
Applying tensile stress in the channel length direction and compressive stress in the channel width direction to the channel area, with a gate electrode and cap portion having compressive stress, to enhance electron mobility and current driving performance
Data Source
AI summary
According to one embodiment, a semiconductor device includes a semiconductor substrate having a trench and including an active area including a channel area formed along an inner surface of the trench and source/drain areas formed at both ends of the channel area and sandwiching the trench, a gate insulating film formed on the inner surface of the trench, and a gate electrode formed in the trench in which the gate insulating film is provided. A main surface of the semiconductor substrate has {100} plane orientation, a portion of the channel area parallel to a side surface of the trench has {110} channel plane orientation and has <100> channel orientation in a channel length direction, and tensile stress in the channel length direction and compressive stress in a channel width direction are applied to the portion of the channel area parallel to the side surface of the trench.