Buried Gate MOS Transistor Non-Uniform Dielectric
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-voltage MOS transistors with planar extended drain structures face breakdown issues due to uniform and thin gate dielectric layers, leading to increased cost and silicon footprint, especially when subjected to high voltages.
Innovation Solution
The implementation of a buried gate MOS transistor with non-uniform gate dielectric dimensions, featuring a thicker upper dielectric zone between the drain and gate regions and a thinner lower dielectric zone between the channel and gate, reducing the risk of breakdown and silicon footprint while maintaining electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a uniform and thin gate dielectric layer is used in planar extended drain structures, then the transistor can be manufactured with simpler processes, but the risk of breakdown increases due to electric field crowding near the drain
Solution Approach 1:
The patent applies local quality by creating a non-uniform gate dielectric layer where the thickness varies spatially: thinner near the source for good electrical performance and thicker near the drain for breakdown protection. This is achieved through selective deposition or etching processes that modify the dielectric thickness in specific regions, allowing each part of the transistor to have optimized properties for its local function.
2Reliability
If a planar extended drain structure is used to achieve high breakdown voltage, then the transistor can handle high voltages, but the silicon footprint increases significantly
Solution Approach 1:
The patent transitions from a planar two-dimensional structure to a three-dimensional vertically-stacked structure. The gate electrode is positioned above the channel region rather than adjacent to it, allowing the transistor to achieve high breakdown voltage through vertical field control rather than horizontal extension. This dimensional change reduces the lateral silicon footprint while maintaining or improving electrical performance.
3Productivity
If the gate dielectric layer is made thinner to improve electrical performance, then the transistor operates more efficiently, but the risk of breakdown near the drain increases
Solution Approach 1:
The gate dielectric layer has different thicknesses at different locations: a first thickness in the source region optimized for electrical performance and a second, greater thickness in the drain region optimized for breakdown protection. This spatial variation in dielectric quality allows the transistor to simultaneously achieve both efficient operation and high voltage tolerance.
Data Source
AI summary
An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate.