Buried Gate Structure Low Resistance Nucleation Layer

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Solution Overview

Problem

Conventional buried gate structures in semiconductor devices often have high resistance due to the β crystalline phase of tungsten, leading to poor electrical characteristics, especially when the design rule is below 20 nm, as the gate electrode may not be properly formed on the metal barrier layer, resulting in increased resistance and suboptimal device performance.

Innovation Solution

A method of manufacturing a semiconductor device with a buried gate structure that includes a low resistance nucleation layer, where a preliminary nucleation layer with a β crystalline phase is thermally treated to convert it into an α crystalline phase, reducing the specific resistance and enhancing the conductive layer's properties, thereby forming a buried gate structure with improved electrical characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the gate electrode is directly formed on the metal barrier layer pattern, then the manufacturing process is simplified, but the gate electrode has high resistance due to the β crystalline phase of tungsten

Engineering Contradiction:

Improvemanufacturing process simplicityVSAvoidelectrical characteristics

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent introduces a preliminary nucleation layer as an intermediary between the metal barrier layer and the conductive layer. This preliminary nucleation layer is then converted to a nucleation layer through thermal treatment, which serves as a mediating structure that enables the conductive layer to achieve low resistance while maintaining proper formation on the barrier layer.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies thermal treatment to change the physical state of the preliminary nucleation layer, converting it from a high-resistance β crystalline phase to a low-resistance state. This parameter change in the nucleation layer's crystalline structure enables the conductive layer to achieve low resistance without complicating the overall manufacturing process.

Inventive Principle:

Principle #35Parameter changes

2Area of moving object

If the design rule is decreased to increase integration density, then the device size is reduced, but the gate electrode resistance increases due to improper formation on the metal barrier layer

Engineering Contradiction:

Improveunit cell sizeVSAvoidelectrical characteristics

Core Design Contradiction:

Area of moving objectVSReliability

Solution Approach 1:

The patent performs preliminary action by forming and thermally treating the preliminary nucleation layer before depositing the conductive layer. This preliminary preparation of the nucleation layer ensures proper adhesion and low resistance properties are established in advance, enabling the gate electrode to maintain low resistance even when the design rule is reduced for higher integration density.

Inventive Principle:

Principle #10Preliminary action

3Ease of manufacture

If the gate electrode includes tungsten of the β crystalline phase, then the manufacturing process is simpler, but the specific resistance is relatively large

Engineering Contradiction:

Improvegate electrode formationVSAvoidspecific resistance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent utilizes phase transition of the nucleation layer material from β crystalline phase to α crystalline phase through thermal treatment. This phase transition fundamentally changes the electrical properties of the nucleation layer, enabling low resistance while maintaining ease of manufacture through a single thermal processing step.

Inventive Principle:

Principle #36Phase transitions

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The approach results in a semiconductor device with enhanced electrical and operational characteristics by reducing the specific resistance of the buried gate structure, maintaining low resistance even at fine design rules below 20 nm, thus improving the overall performance of the semiconductor device.

Implementation Method 1

The preliminary nucleation layer is converted to a nucleation layer having a second resistance that is substantially smaller than the first resistance

Methodology Applied

Scientific EffectPhase transition: Phase Change

Implementation Method 2

the preliminary nucleation layer may include a metal and the nucleation layer may be formed by thermally treating the preliminary nucleation layer

Methodology Applied

Scientific EffectThermal treatment: Heat Treatment

Data Source

PatentUS8168521B2Methods of manufacturing semiconductor devices having low resistance buried gate structures

Publication Date: 2012.05.01 SAMSUNG ELECTRONICS CO LTD

AI summary

In a method of manufacturing a semiconductor device, a recess is formed in an active region of a substrate. A gate insulation layer is formed in the first recess. A barrier layer is formed on the gate insulation layer. A preliminary nucleation layer having a first resistance is formed on the barrier layer. The preliminary nucleation layer is converted into a nucleation layer having a second resistance substantially smaller than the first resistance. A conductive layer is formed on the nucleation layer. The conductive layer, the nucleation layer, the barrier layer and the gate insulation layer are partially etched to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern.