Buried Gate Overlap Control for Leakage Reduction
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Solution Overview
Problem
The existing semiconductor devices face issues such as increased leakage current due to Gate Induced Drain Leakage (GIDL), deteriorated refresh characteristics, and increased parasitic capacitance, which affect the operational reliability and speed, particularly in buried word line structures with small overlap regions between the buried gate and junction.
Innovation Solution
A semiconductor device and manufacturing method that forms a gate electrode material in a recess, with a polysilicon pattern doped with impurities at the sidewall of the recess, and uses an annealing or rapid thermal annealing process to adjust the overlap thickness between the buried gate and junction, thereby reducing GIDL and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a buried word line structure is used to reduce parasitic capacitance, then parasitic capacitance between bit line and word line is reduced, but leakage current due to GIDL is increased
Solution Approach 1:
The patent applies different properties to different regions: the buried word line structure is used in regions where parasitic capacitance reduction is critical, while the junction depth and doping concentration are locally adjusted in specific areas to control GIDL. The selective etching and annealing processes create localized variations in overlap thickness to balance these two harmful effects.
Solution Approach 2:
The patent changes physical parameters such as junction depth, doping concentration, and overlap thickness through controlled annealing processes. By adjusting these parameters, the patent optimizes the balance between reducing parasitic capacitance and minimizing GIDL-induced leakage current in the buried word line structure.
2Object-generated harmful factors
If large amounts of conductive material are etched to minimize overlap region and prevent GIDL, then leakage current is reduced, but resistance of buried word line increases
Solution Approach 1:
The patent applies partial etching to create a controlled overlap region rather than completely removing the conductive material. This partial action allows maintaining sufficient conductivity while reducing GIDL effects, avoiding the excessive etching that would cause both low leakage and high resistance.
Solution Approach 2:
The patent performs preliminary doping and annealing processes before final etching to pre-establish the electrical properties of the buried word line. This preliminary action ensures that even after etching reduces the overlap region, the remaining structure maintains adequate conductivity for acceptable operation speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes leakage current, maintains refresh characteristics, and reduces parasitic capacitance, enhancing the operational reliability and speed of semiconductor devices by optimizing the overlap region between the buried gate and junction.
Implementation Method 1
a junction formed using an annealing or a rapid thermal annealing (RTA) process
Implementation Method 2
a junction formed using an annealing or a rapid thermal annealing (RTA) process
Implementation Method 3
a polysilicon material doped with impurities over a sidewall of a recess located over the gate electrode material
Data Source
AI summary
A semiconductor device and a method for manufacturing the same are disclosed, which include a gate electrode material in a recess or a buried gate cell structure, a polysilicon material doped with impurities over a sidewall of a recess located over the gate electrode material, and a junction formed by an annealing or a rapid thermal annealing (RTA) process, thereby establishing a degree overlap between a gate electrode material of a buried gate and a junction.