Buried-Gate Pixel Transistor Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The parasitic capacitance of the gate in CMOS image sensors with buried gate structures increases, leading to a deterioration in signal-to-noise ratio and conversion efficiency, which affects the performance of pixel transistors.
Innovation Solution
A solid-state imaging element design featuring a Fin-type transistor with a gate electrode structure that includes a first gate electrode portion embedded in the substrate, a second gate electrode portion electrically connected to the first, and an upper gate electrode portion connecting them, with specific insulating films to reduce parasitic capacitance and enhance channel area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a buried gate structure is used to increase channel area, then noise is reduced and reading speed is improved, but parasitic capacitance of the gate increases and signal-to-noise ratio deteriorates
Solution Approach 1:
The gate insulating film thickness is varied locally: it is set to a first thickness (5 nm to 20 nm) in the channel formation region and a second thickness (20 nm to 50 nm) in regions where the gate electrode contacts the semiconductor substrate. This local differentiation maintains a thin gate insulating film where needed for channel formation while providing a thick gate insulating film at contact regions to reduce parasitic capacitance between the gate electrode and substrate.
Solution Approach 2:
The invention transitions from a conventional planar gate structure to a three-dimensional buried gate structure where the gate electrode is embedded in trenches formed in the semiconductor substrate. This dimensional change allows the gate to extend vertically and laterally, increasing channel area while the thick gate insulating film at the substrate interface controls parasitic capacitance.
2Productivity
If the gate insulating film is made thinner to improve transistor performance, then conversion efficiency improves, but parasitic capacitance increases and signal-to-noise ratio deteriorates
Solution Approach 1:
The gate insulating film thickness is differentiated into two regions: a thin region (5 nm to 20 nm) over the channel formation region to ensure good transistor performance and conversion efficiency, and a thick region (20 nm to 50 nm) where the gate electrode contacts the semiconductor substrate to minimize parasitic capacitance. This local quality variation resolves the contradiction between conversion efficiency and parasitic capacitance.
3Speed
If the gate electrode is embedded deeper in the substrate to increase channel area, then reading speed improves, but parasitic capacitance between gate and substrate increases
Solution Approach 1:
The gate insulating film is formed with a thickness gradient: thinner (5 nm to 20 nm) in the channel region to maintain electrical performance and thicker (20 nm to 50 nm) at the substrate contact regions. This allows the gate electrode to be embedded deeply for increased channel area and improved reading speed, while the thick gate insulating film at the interface suppresses parasitic capacitance between the gate and substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces parasitic capacitance, improving the signal-to-noise ratio and conversion efficiency while increasing the operational speed of the amplification transistor, allowing for better light conversion and image sensing.
Implementation Method 1
when a parasitic capacitance of the gate of the amplification transistor increases, conversion efficiency at the time of amplifying the pixel charge decreases, and the signal/noise (S/N) ratio deteriorates
Implementation Method 2
A solid-state imaging element includes a plurality of pixels that photoelectrically converts incident light
Data Source
AI summary
There is provided a solid-state imaging element capable of increasing a channel area of a pixel transistor and reducing a parasitic capacitance of a gate. A solid-state imaging element is a solid-state imaging element including pixels that photoelectrically convert incident light, and includes a substrate on which the pixels are provided, a first transistor provided in the pixels and including a first gate electrode portion embedded in a first direction from a first surface of the substrate toward a second surface of the substrate opposite to the first surface, a first gate insulating film provided between an active region of the substrate in which a channel of the first transistor is formed and a first side surface of the first gate electrode portion facing the active region, and a first insulating film provided on a second side surface of the first gate electrode portion other than the first side surface and thicker than the first gate insulating film, in which a depth of the first insulating film from the first surface to the second surface of the substrate is substantially the same as or deeper than a depth of the first gate electrode portion, and a width of an upper surface of the first gate electrode portion is wider than a width of a bottom surface of the first gate electrode portion in a cross section in the first direction.