Buried Gate Fin Structure for Row Hammer Suppression
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Solution Overview
Problem
The integration of semiconductor devices with buried gates faces reliability issues due to row hammer phenomena, which cause data distortion and Gate-Induced Drain Leakage (GIDL), primarily attributed to the influence of passing gates on adjacent capacitors.
Innovation Solution
The semiconductor device design incorporates a buried gate structure with fin gates, active gates, and passing gates, where the bottom surfaces of passing gates are higher than active gates, and fin gates are lower, along with a dipole inducing layer and a work function adjusting element to reduce the effective work function, thereby minimizing row hammer effects and GIDL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a buried gate structure is used to increase integration degree, then device density is improved, but reliability deteriorates due to row hammer phenomena and increased resistance
Solution Approach 1:
The patent applies asymmetry by forming active fins with different heights (first active fins taller than second active fins) and configuring passing gates at different levels relative to active gates. This asymmetric structure prevents uniform electron migration paths that cause row hammer phenomena, thereby maintaining reliability while preserving the high integration benefits of the buried gate structure.
Solution Approach 2:
The patent implements local quality by creating different fin heights in different regions (first active fins vs. second active fins) and positioning passing gates at different levels over different isolation regions. This localized variation in structure prevents widespread electron migration and trap formation, addressing reliability issues while maintaining overall device density.
2Ease of manufacture
If passing gates are formed at the same level as active gates, then manufacturing is simplified, but electron migration increases causing row hammer phenomena
Solution Approach 1:
The patent deliberately creates asymmetry in gate positioning by forming passing gates at different levels than active gates. Specifically, passing gates over first isolation portions are positioned at a first level while passing gates over second isolation portions are positioned at a second level. This asymmetric configuration disrupts electron migration paths and prevents row hammer phenomena while remaining manufacturable through selective etching and filling processes.
3Reliability
If fin gates extend deeper than active gates, then channel control is improved, but manufacturing complexity increases due to stepped trench profile
Solution Approach 1:
The patent applies segmentation by dividing the gate trench into multiple sections with different depths corresponding to different gate functions. The trench has a stepped profile where fin gates extend to a first depth, active gates extend to a second depth, and passing gates extend to a third depth. This segmented approach allows each gate type to optimize its channel control while the stepped structure itself becomes a manageable manufacturing feature rather than a complexity burden.
4Ease of manufacture
If uniform active fins are used, then manufacturing is easier, but driving current is reduced due to insufficient channel formation
Solution Approach 1:
The patent implements asymmetry by forming two sets of active fins with different heights: first active fins that are taller and second active fins that are shorter. This asymmetric fin structure creates varied channel lengths and cross-sections that enhance driving current by optimizing charge carrier flow paths. The different fin heights can be achieved through selective epitaxial growth or selective removal, processes that add minimal manufacturing complexity while significantly improving electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability of semiconductor devices by reducing resistance and maintaining refresh rates, while the asymmetric channel structure and dielectric dummy electrodes further suppress row hammering, improving operational characteristics and driving current.
Implementation Method 1
a dipole inducing layer between the first gate electrode and the second gate electrode
Data Source
AI summary
A semiconductor device includes: an isolation layer formed to define active regions including active fins in a substrate; gate trenches extending across the active fins and the isolation layer; and buried gates that fill the gate trenches, and include fin gates disposed on sidewalls of the active fins, active gates disposed over the active fins, and passing gates disposed over the isolation layer, wherein bottom surfaces of the passing gates are disposed at a higher level than bottom surfaces of the active gates, and bottom surfaces of the fin gates are disposed at a lower level than the bottom surfaces of the active gates.