Buried Gate Fabrication via Sealing Layer Protection
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Solution Overview
Problem
Conventional semiconductor device fabrication methods employing buried gates face challenges in achieving satisfactory device characteristics and reliability due to protrusions formed at the boundary between cell and peripheral regions, leading to structural damage and process complexities.
Innovation Solution
The method involves forming a peripheral gate conductive layer in the peripheral regions before forming plugs in the cell regions, using a sealing layer to protect the structure during planarization and etching processes, thereby preventing protrusions and simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional method is used to form bit line contact holes and peripheral gates sequentially, then the device structure can be formed, but protrusions are created at the boundary between cell and peripheral regions causing structural damage and reliability issues
Solution Approach 1:
The peripheral gate conductive layer is formed in advance before the plug formation process. This preliminary action ensures that the peripheral gate structure is already in place before etching and planarization processes, preventing protrusion formation at the boundary regions and eliminating the need for complex post-processing steps to remove defects
Solution Approach 2:
The fabrication process is segmented into distinct stages: first forming the peripheral gate conductive layer, then forming plugs in cell regions, and finally performing planarization. This segmentation allows each process to be optimized independently and avoids the interference that causes protrusions when processes are performed in conventional sequence
2Ease of manufacture
If the peripheral gate conductive layer is formed after plug formation, then the process follows conventional sequence, but protrusions form at region boundaries requiring additional planarization steps
Solution Approach 1:
The peripheral gate conductive layer is formed preliminarily before plug formation and etching processes. This ensures that when subsequent etching and planarization are performed, the peripheral gate structure serves as a stable reference that prevents protrusion formation at boundaries, maintaining both process simplicity and boundary precision
Solution Approach 2:
The peripheral gate conductive layer acts as a protective cushion formed beforehand that prevents damage to the boundary region during subsequent etching and planarization processes. This preliminary protective structure absorbs the mechanical stress and prevents protrusion formation that would otherwise occur at the vulnerable boundary between cell and peripheral regions
Data Source
AI summary
A method for fabricating a semiconductor device includes providing a substrate including cell regions and peripheral regions; selectively forming a gate conductive layer over the substrate in the peripheral regions, forming a sealing layer over the substrate with the gate conductive layer formed thereon, forming an insulation layer over the sealing layer to cover the substrate with the gate conductive layer formed on the substrate, planarizing the insulation layer to expose the sealing layer formed over the gate conductive layer, and forming a plurality of plugs in the cell regions, the plurality of the plugs penetrating the insulation layer and the sealing layer.