Buried Gate Semiconductor Device With Embedded Bit Line
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Solution Overview
Problem
Conventional semiconductor device fabrication techniques face challenges in achieving desired device characteristics due to technical limitations in forming gate structures, bit lines, and contact structures, particularly with design rules below 40 nm, leading to increased procedural complexity and damage to the substrate structure from step heights between cell and peripheral regions.
Innovation Solution
A semiconductor device with buried gates is fabricated by forming a peripheral bit line inside the inter-layer dielectric layer, eliminating the step height between cell and peripheral regions, and using a method that includes forming a damascene pattern to expose the conductive layer and filling it with a bit line, thereby simplifying subsequent processes and protecting the etch stop layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the peripheral bit line is formed over the inter-layer dielectric layer in the peripheral region, then the peripheral gate can be contacted, but step height is formed between cell and peripheral regions causing procedural complexity and substrate damage
Solution Approach 1:
The peripheral bit line is repositioned from the upper surface of the inter-layer dielectric layer to the interior of the inter-layer dielectric layer. This dimensional change eliminates step height formation between cell and peripheral regions, as the bit line is now embedded within the dielectric material rather than sitting on top of it, thereby simplifying subsequent fabrication processes and protecting the substrate structure.
2Ease of manufacture
If the peripheral bit line is formed over the inter-layer dielectric layer, then contact with peripheral gate is achieved, but step height cracks the etch stop layer and damages substrate structure
Solution Approach 1:
The peripheral bit line is moved from the upper surface to the interior of the inter-layer dielectric layer. This repositioning eliminates the step height that causes mechanical stress and cracking in the etch stop layer, while still achieving proper contact with the peripheral gate electrode through the damascene process.
3Reliability
If conventional bit line formation is used, then peripheral gate contact is achieved, but subsequent processes become complex and procedurally difficult
Solution Approach 1:
By forming the peripheral bit line inside the inter-layer dielectric layer rather than on its surface, the invention eliminates step height formation. This enables subsequent fabrication processes to proceed without the procedural complexity and difficulty associated with managing step heights, thereby improving overall fabrication efficiency while maintaining reliable gate contact.
Data Source
AI summary
A semiconductor device includes a substrate having a cell region and a peripheral region, a buried gate formed over the substrate of the cell region, a peripheral gate formed over the substrate of the peripheral region and comprising a conductive layer, an inter-layer dielectric layer that covers the substrate, and a peripheral bit line formed inside the inter-layer dielectric layer and contacting the conductive layer.