Buried Gate Semiconductor Device Mitigating GIDL
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices become more highly integrated and have larger capacities, their electric characteristics deteriorate due to short channel effects, particularly generating gate-induced drain leakage (GIDL) in thin film transistors, which is exacerbated by the shortening channel length.
Innovation Solution
A semiconductor device with a buried gate structure is developed, featuring isolation layers and an insulation layer pattern that applies stress to the substrate, enhancing electrical characteristics by optimizing the geometry and material properties of the gate structure and insulation layers to mitigate the short channel effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length is shortened to increase integration density, then device capacity increases, but gate-induced drain leakage (GIDL) worsens due to short channel effects
Solution Approach 1:
The patent introduces a buried gate structure that extends vertically into the substrate, adding a depth dimension to the traditional planar gate. This three-dimensional gate configuration allows the channel length to be effectively increased in the vertical direction while maintaining a short horizontal channel length, thereby achieving high integration density without suffering from severe short channel effects and GIDL.
Solution Approach 2:
The patent applies different isolation layer configurations to different regions: a first isolation layer in the peripheral region and a second isolation layer in the cell region. Additionally, the insulation layer pattern is selectively positioned to apply stress specifically to the channel region beneath the gate, optimizing electrical characteristics locally where needed without affecting other device regions.
2Reliability
If the channel length is increased by forming a buried gate structure, then short channel effects are mitigated, but device area increases
Solution Approach 1:
The buried gate structure utilizes the vertical dimension by extending the gate into the substrate depth, effectively increasing the channel length in the vertical direction. This allows the horizontal device footprint to remain compact while achieving the electrical performance benefits of a longer channel, thus resolving the contradiction between reliability and device area.
Solution Approach 2:
The gate structure is nested within the substrate by forming a trench and filling it with conductive material, creating a buried gate configuration. This nested structure allows the channel to extend vertically within the substrate volume rather than requiring additional horizontal space, thereby improving electrical characteristics without significantly increasing the device footprint.
3Reliability
If an insulation layer pattern is added to apply stress to the substrate, then charge mobility improves, but manufacturing complexity increases
Solution Approach 1:
The insulation layer pattern is formed by combining multiple materials (first and second insulation materials with different stress properties) into a single integrated structure. This merged structure serves multiple functions: electrical isolation and stress application, thereby improving charge mobility without requiring separate manufacturing processes for each function, thus limiting the increase in manufacturing complexity.
Solution Approach 2:
The patent utilizes changes in material parameters (different insulation materials with different stress characteristics) to achieve the desired stress application. By selecting materials with appropriate thermal expansion coefficients or intrinsic stress properties, the insulation layer pattern can apply tensile or compressive stress to the substrate to enhance charge mobility, achieving performance improvement through material parameter optimization rather than complex structural changes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the electrical characteristics of semiconductor devices by reducing gate-induced drain leakage and enhancing charge mobility through the application of stress by the insulation layer pattern, effectively addressing the short channel effect and improving device performance.
Implementation Method 1
The insulation layer pattern has a lower surface higher than a lower surface of the second isolation layer, and applies a stress to a portion of the substrate adjacent thereto
Data Source
AI summary
A semiconductor device includes a substrate, first and second isolation layers, an insulation layer pattern, and a gate structure. The substrate has a cell region and a peripheral region. The first isolation layer is buried in a first upper portion of the substrate in the peripheral region. The second isolation layer is buried in a second upper portion of the substrate in the cell region, and extends along a first direction substantially parallel to a top surface of the substrate. The insulation layer pattern is buried in the first upper portion, and extends along a second direction substantially parallel to the top surface of the substrate and substantially perpendicular to the first direction. The insulation layer pattern has a lower surface higher than a lower surface of the second isolation layer, and applies a stress to a portion of the substrate adjacent thereto.