Buried-Gate Active Area Layout for Semiconductor Isolation
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Solution Overview
Problem
The miniaturization of semiconductor devices poses challenges in maintaining performance and achieving effective insulation between small active areas, as the manufacturing process faces restrictions due to reduced spacing and width of active areas, leading to issues like short-circuits, dislocations, and current leakage.
Innovation Solution
A semiconductor device is designed with a mask layer defining active areas having a wider top and narrower bottom cross-section, and shallow trench isolation with a narrower top and wider bottom cross-section, ensuring effective isolation and maintaining integration levels, using techniques like selective epitaxial growth and etch-back processes to form insulating layers and buried gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the width and spacing of active areas are reduced to achieve miniaturization, then the integration level is improved, but the insulation effect between adjacent active areas deteriorates
Solution Approach 1:
The patent applies asymmetry by giving the shallow trench isolation a trapezoidal cross-section that is narrower at the top and wider at the bottom, opposite to the active area profile. This asymmetric design allows the isolation width at the bottom to be sufficient for insulation even when top widths are reduced for miniaturization, resolving the contradiction between integration level and insulation effect
Solution Approach 2:
The patent inverts the typical profile relationship between active areas and isolation structures. Instead of both having uniform or similarly tapered profiles, the shallow trench isolation is designed with a reverse trapezoidal profile (narrower at top, wider at bottom) compared to the active area profile (wider at top, narrower at bottom), enabling effective insulation at reduced dimensions
2Length of moving object
If the spacing between active areas is reduced for miniaturization, then the device size is decreased, but short-circuits and current leakage occur
Solution Approach 1:
The asymmetric trapezoidal profile of the shallow trench isolation with wider bottom provides sufficient electrical isolation at the critical interface region even when top spacing is reduced, preventing short-circuits and current leakage while enabling miniaturization
Solution Approach 2:
The patent applies local quality by concentrating the isolation function at the bottom interface region where the wider trapezoidal profile provides enhanced electrical isolation, while the top region can be narrower to accommodate miniaturization requirements
Data Source
AI summary
A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, a plurality of active areas, a shallow trench isolation and a plurality of buried gates. The active areas are formed on the substrate, wherein each active area includes a semiconductor layer, and a first interface exists between the semiconductor layer and the substrate. The shallow trench isolation is disposed on the substrate and surrounds the active areas. Each buried gates is buried in one of the plurality of active areas and disposed above the first interface. Accordingly, the isolation effect between the active areas can be enhanced on the condition of maintaining a certain level of integration. Meanwhile, the possible device defects derived from the raised level of integration can be ameliorated.