Buried Gate Semiconductor Structure Mitigating Short-Channel Effects
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Solution Overview
Problem
As semiconductor devices are scaled down, they can experience short-channel effects such as drain-induced barrier lowering and hot carrier degradation, which affect their performance and reliability, and traditional methods to enhance performance like strained silicon may not be sufficient to address these issues effectively.
Innovation Solution
The semiconductor structure incorporates a buried gate and stressors in pattern-dense and pattern-loose regions, with strained silicon germanium layers to increase interatomic distance and improve carrier mobility, combined with a planar gate structure in the pattern-loose region, to mitigate short-channel effects and enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the channel length of MOSFET is scaled down to improve device density and capacity, then device size is reduced, but short-channel effects such as drain-induced barrier lowering and hot carrier degradation occur
Solution Approach 1:
The gate structure is segmented into two distinct types: buried gates in pattern-dense regions and planar gates in pattern-loose regions. This segmentation allows each gate type to be optimized for its specific region's requirements, with buried gates providing better short-channel control in dense areas where device density is critical.
Solution Approach 2:
Different gate structures are applied to different regions of the substrate based on local requirements. Pattern-dense regions receive buried gates with specific trench depths and configurations optimized for short-channel control, while pattern-loose regions receive planar gates. This local quality approach ensures that each region receives the appropriate gate structure for its specific needs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces short-channel effects, improves carrier mobility, and results in semiconductor devices with better performance, lower energy consumption, and greater reliability by carefully designing the gate trench and using stressors to create strained silicon layers.
Implementation Method 1
Strained silicon is a layer of silicon in which the silicon atoms are stretched beyond their normal interatomic distance. Moving these silicon atoms farther apart reduces the atomic forces that interfere with the movement of electrons through the transistors and thus improves carrier mobility
Data Source
AI summary
The present disclosure provides a semiconductor structure and a method for preparing the semiconductor structure. The semiconductor structure includes a substrate having a pattern-dense region and a pattern-loose region; a first drain stressor disposed in the pattern-dense region; a first source stressor disposed in the pattern-dense region; a buried gate structure disposed in the pattern-dense region, between the first drain stressor and the first source stressor; a second drain stressor disposed in the pattern-loose region; a second source stressor disposed in the pattern-loose region; and a planar gate structure disposed in the pattern-loose region, between the second drain stressor and the second source stressor.