Buried Gate Trench Structure for DRAM Short-Channel Control
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Solution Overview
Problem
The reduction in size of dynamic random access memories (DRAMs) leads to a short channel effect, characterized by decreased threshold voltage, reduced operating current, enhanced hot carrier effect, and inability to turn off the device due to degraded threshold characteristics.
Innovation Solution
A buried gate manufacturing method involving the formation of concave structures on the surface of the word line trench and a conductive layer with convex structures matched to the concave structures, increasing the length of the gate channel without altering the width of the word line trench.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the device size is reduced to improve integration, then the integration density increases, but the gate channel length becomes shorter causing short channel effect
Solution Approach 1:
The patent introduces a vertical dimension by forming concave structures on the word line trench surface and matching convex structures on the conductive layer. This transforms the traditionally planar gate channel into a three-dimensional structure with increased surface area, effectively increasing the gate channel length in the vertical direction while maintaining the same horizontal device footprint, thus resolving the contradiction between device size reduction and gate channel length maintenance
2Reliability
If the gate channel length is increased to reduce short channel effect, then the device performance improves, but the device area increases
Solution Approach 1:
By utilizing the vertical dimension through concave-convex structures, the patent achieves increased gate channel length without expanding the horizontal device area. The concave structures on the word line trench surface and matching convex structures on the conductive layer create additional gate channel path length in the vertical direction, improving device performance while maintaining compact device footprint
3Length of moving object
If the word line trench width is increased to accommodate longer gate channel, then the gate channel length increases, but the integration density decreases
Solution Approach 1:
The patent resolves this contradiction by transitioning from a two-dimensional planar gate channel to a three-dimensional structure. The concave structures formed on the word line trench surface and matching convex structures on the conductive layer extend the gate channel length vertically, allowing the gate channel to be longer without increasing the horizontal width of the word line trench, thus maintaining high integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively addresses the short channel effect by increasing the gate channel length, thereby improving device performance and reducing the impact of device size reduction.
Implementation Method 1
The hemispherical silicon crystal particles are formed by an LPCVD process, in the LPCVD process, a reaction gas comprises SiH4, a reaction temperature ranges from 500° C. to 600° C., and a reaction pressure ranges from 0.1 torr to 0.5 torr.
Data Source
AI summary
A method for manufacturing a buried gate includes: providing a substrate; forming a word line trench in the substrate; treating a surface of the word line trench to form concave structures on the surface of the word line trench; and, forming a conductive layer in the word line trench, convex structures matched with the concave structures being provided on a surface of the conductive layer.