Buried Gate Semiconductor Structure to Prevent Gate-Source Shorts
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Solution Overview
Problem
Semiconductor devices face defects such as gate-source short circuits and channel non-formation due to etch process deviations, particularly in buried gate structures, which affect yield and require complex process adjustments.
Innovation Solution
The solution involves removing the gate protruding portion during the formation of a buried gate structure, allowing for intentional over-etching to prevent short circuits and ensure proper channel formation without requiring new process technologies or increasing costs, by aligning the N+ type region surfaces with the gate electrode surfaces through ion implantation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a buried gate structure is formed with gate polysilicon, then on-resistance is reduced and current density is improved, but gate-source short circuits may occur and channel non-formation can result from etch process deviation
Solution Approach 1:
The gate protruding portion is selectively removed through etch process deviation, extracting the harmful element that causes gate-source short circuits while preserving the beneficial buried gate structure. This resolves the contradiction by removing the specific defect-causing feature without eliminating the overall improved electrical characteristics.
Solution Approach 2:
The etch process parameters are intentionally deviated to achieve selective removal of the gate protruding portion. By changing the etch conditions, the process selectively targets and removes the problematic protrusion while maintaining the desired buried gate structure, thereby improving reliability without sacrificing the low on-resistance benefit.
2Ease of manufacture
If etch process deviation occurs during buried gate formation, then manufacturing simplicity is maintained, but channel non-formation defects arise
Solution Approach 1:
The etch process deviation, which initially causes channel non-formation defects, is converted into a beneficial process that selectively removes the gate protruding portion. The same process variability that creates problems is harnessed to eliminate the harmful protrusion, thereby improving both manufacturing simplicity and channel formation accuracy simultaneously.
3Reliability
If additional processes are implemented to prevent gate-source short circuits, then reliability improves, but process complexity and costs increase
Solution Approach 1:
The etch process itself performs the dual function of forming the buried gate structure and selectively removing the gate protruding portion that causes short circuits. The process serves itself by using its inherent variability to eliminate defects, eliminating the need for additional corrective processes and maintaining process simplicity while improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device yield by preventing short circuits and ensuring channel formation, increasing the semiconductor device's reliability and efficiency without adding new processes or costs.
Implementation Method 1
implanting N type ions into the upper surface of the P type region disposed adjacent to the trench and the exposed side of the trench for forming an N+ type region
Data Source
AI summary
An embodiment semiconductor device includes an N− type layer having a trench therein, a P type region within the N− type layer, an N+ type region within the P type region, a gate electrode within the trench including a first gate electrode having an upper surface lower than an upper surface of the P type region and a second gate electrode having an upper surface lower than the upper surface of the first gate electrode, and source and drain electrodes insulated from the gate electrode, wherein the N+ type region includes a first N+ type region on a side of the first gate electrode and having a lower surface lower than the upper surface of the first gate electrode and a second N+ type region on a side of the second gate electrode and having a lower surface lower than the lower surface of the first N+ type region.