Buried Gate Fabrication for Step Height Reduction
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices with buried gates face challenges in minimizing the step height difference between the cell and core/peri regions, leading to issues with excessive poly deposition and increased complexity in the fabrication process, especially at advanced technology nodes like 40 nm or less.
Innovation Solution
A method is developed to simplify the fabrication process by forming a gate conductive layer in both the cell and peri regions before creating a bit line contact, using a stacked structure of amorphous carbon and silicon oxide nitride layers, and burying the conductive layer in trenches, which reduces the need for additional processing steps and minimizes interference between the bit line and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a gate conductive layer is formed in both cell and peri regions before creating bit line contact, then the fabrication process is simplified and step height issues are prevented, but the poly deposition becomes excessive in the vicinity of the boundary between regions
Solution Approach 1:
The gate conductive layer is formed in advance in both cell and peri regions before the bit line contact formation. This preliminary action allows the poly parts to be deposited simultaneously and uniformly, preventing excessive deposition at boundaries by establishing the gate structure before the bit line contact is created.
Solution Approach 2:
The fabrication process merges the formation of gate conductive layers in cell and peri regions into a single simultaneous deposition step. By combining these operations and using a unified deposition process, the method eliminates the need for separate deposition steps that would cause excessive poly accumulation at region boundaries.
2Productivity
If bit line and gate are simultaneously formed, then the fabrication process is simplified, but excessive poly deposition occurs at the boundary between cell and core/peri regions causing various problems
Solution Approach 1:
The gate conductive layer is formed preliminarily in both regions before bit line contact formation. This sequencing ensures that when poly is deposited, both gate and bit line structures are already in place, allowing for uniform deposition without excessive accumulation at boundaries.
Solution Approach 2:
The method changes the deposition parameters and timing by forming the gate conductive layer at a specific stage before bit line contact formation. This parameter change in the fabrication sequence allows for controlled poly deposition that prevents excessive accumulation while maintaining simultaneous formation efficiency.
3Object-generated harmful factors
If a trench is formed to bury the gate in the cell region, then interference between bit line and gate is minimized and capacitance is decreased, but a step height difference is created between cell and core/peri regions
Solution Approach 1:
The trench structure is applied locally only in the cell region where the buried gate is needed to reduce capacitance and interference. The core/peri region maintains its original planar structure, creating a localized solution that addresses the specific problem in the cell region without affecting other areas.
Solution Approach 2:
The gate structure transitions from a planar configuration to a three-dimensional buried configuration within the trench. By moving the gate into the substrate dimension, the method reduces the step height impact on the bit line while maintaining electrical isolation and reducing capacitance in the cell region.
Data Source
AI summary
A method for manufacturing a semiconductor device having a buried gate is provided. A gate conductive layer is first formed in the peri region before a bit line contact is formed in the cell region, so that a fabrication process is simplified and the problem caused by a step height between the cell region and the core/peri region is not encountered.