Buried Gate Semiconductor Device with Stepped Electrode

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Solution Overview

Problem

Buried gate semiconductor devices face increased gate-induced drain leakage (GIDL) which degrades refresh characteristics and increases resistance, compromising device performance and reliability.

Innovation Solution

A semiconductor device with a trench structure featuring a first gate electrode with a stepped upper surface and a second gate electrode overlapping the junction regions, along with a nitrogen-containing barrier layer between them, to minimize GIDL and reduce gate resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If the conductive material (gate electrode) of the buried gate is over-etched to minimize overlapping area between the storage node contact and the gate conductive material, then GIDL is reduced, but resistance of the buried gate increases and current driving capability is lowered

Engineering Contradiction:
ImproveGIDLVSAvoidcurrent driving capability
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The gate electrode is divided into two distinct parts: a first gate electrode made of conductive material (such as tungsten or copper) and a second gate electrode made of polysilicon. The first gate electrode extends to minimize overlapping with storage node contacts, while the second gate electrode is positioned to maintain electrical connection and current driving capability. This segmentation allows each part to fulfill its specific function without compromising the other.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different materials are used for different parts of the gate electrode structure. The first gate electrode uses highly conductive material (tungsten or copper) for minimal resistance and optimal current driving, while the second gate electrode uses polysilicon which provides good gate control and can be doped to achieve desired electrical characteristics. This local differentiation of material properties optimizes both GIDL reduction and current driving capability in their respective regions.

Inventive Principle:
Principle #3Local quality

2Object-generated harmful factors

If the conductive material (gate electrode) of the buried gate is over-etched to minimize overlapping area between the storage node contact and the gate conductive material, then GIDL is reduced, but speed of the semiconductor device is lowered

Engineering Contradiction:
ImproveGIDLVSAvoiddevice speed
Core Design Contradiction:
Object-generated harmful factorsVSSpeed

Solution Approach 1:

The gate electrode is divided into two distinct parts: a first gate electrode made of conductive material (such as tungsten or copper) and a second gate electrode made of polysilicon. The first gate electrode extends to minimize overlapping with storage node contacts, while the second gate electrode is positioned to maintain electrical connection and current driving capability. This segmentation allows each part to fulfill its specific function without compromising the other.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different materials are used for different parts of the gate electrode structure. The first gate electrode uses highly conductive material (tungsten or copper) for minimal resistance and optimal current driving, while the second gate electrode uses polysilicon which provides good gate control and can be doped to achieve desired electrical characteristics. This local differentiation of material properties optimizes both GIDL reduction and current driving capability in their respective regions.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9356029B2Semiconductor device having buried gate, method of fabricating the same, and module and system having the same
Publication Date: 2016.05.31 SK HYNIX INC
  • US9356029B2 patent drawing
  • US9356029B2 patent drawing
  • US9356029B2 patent drawing

AI summary

A semiconductor device includes junction regions formed in upper portions of both sidewalls of a trench formed in a semiconductor substrate, a first gate electrode buried in the trench and having a stepped upper surface, and a second gate electrode formed on the first gate electrode to overlap a junction region.