Buried Gate Transistor GIDL Reduction via Dual Dielectric Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Buried gate type transistors face challenges in controlling gate induced drain leakage (GIDL), which affects their performance, particularly in high-performance operations where threshold voltage control is crucial.
Innovation Solution
A semiconductor device with a buried gate structure is developed, featuring a substrate with doped regions, a trench, a first gate dielectric layer, a lower gate, an upper gate with a smaller width, and a second gate dielectric layer, which helps in reducing GIDL by adjusting the work function and using dual gate dielectric layers to prevent damage from fluorine attack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a buried gate structure is used to control threshold voltage, then transistor performance is improved, but gate induced drain leakage (GIDL) increases
Solution Approach 1:
The gate dielectric layer is divided into two separate layers: a first gate dielectric layer formed at the bottom of the trench and a second gate dielectric layer formed over the first gate dielectric layer. This segmentation allows each layer to serve specific functions - the first layer provides baseline insulation and threshold control, while the second layer specifically addresses GIDL reduction by providing an additional dielectric barrier that prevents harmful electrical interactions between the gate and drain regions.
Solution Approach 2:
The gate dielectric structure uses a composite of two different dielectric layers with potentially different material compositions and properties. This composite structure combines the advantages of each layer - the first gate dielectric layer may provide excellent interface characteristics for threshold voltage control, while the second gate dielectric layer provides superior insulation properties to suppress GIDL, achieving overall performance that neither layer could provide alone.
2Device complexity
If a single gate dielectric layer is used, then device structure is simple, but the gate dielectric layer is damaged by fluorine attack
Solution Approach 1:
The gate dielectric layer is divided into two separate layers: a first gate dielectric layer formed at the bottom of the trench and a second gate dielectric layer formed over the first gate dielectric layer. This segmentation allows each layer to serve specific functions - the first layer provides baseline insulation and threshold control, while the second layer specifically addresses GIDL reduction by providing an additional dielectric barrier that prevents harmful electrical interactions between the gate and drain regions.
Solution Approach 2:
The second gate dielectric layer is formed as a protective layer over the first gate dielectric layer before any fluorine-containing processes are performed. This beforehand cushioning protects the first gate dielectric layer from fluorine attack during subsequent manufacturing steps, preventing damage and maintaining the integrity of the gate dielectric structure throughout the fabrication process.
3Ease of manufacture
If the upper gate has the same width as the lower gate, then manufacturing is easier, but electrical characteristics are suboptimal
Solution Approach 1:
The upper gate is designed with a different width than the lower gate, creating local variation in the gate structure. This local quality change allows optimization of electrical characteristics - the narrower upper gate provides better control over the channel region directly beneath it, improving threshold voltage control and reducing GIDL, while the lower gate maintains sufficient width for overall device performance and manufacturing feasibility.
Data Source
AI summary
Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the semiconductor device includes a substrate, a first doped region and a second doped region formed to be spaced apart from each other by a trench in the substrate, a first gate dielectric layer over the trench, a lower gate over the first gate dielectric layer, an upper gate over the lower gate and having a smaller width than the lower gate, and a second gate dielectric layer between the upper gate and the first gate dielectric layer.