Buried Gate Transistor Structure for DRAM Memory Cell Scaling
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Solution Overview
Problem
As semiconductor fabrication advances, the scaling down of memory devices leads to challenges in gate control ability due to reduced memory cell sizes, resulting in lower saturation current and inferior performance in DRAMs.
Innovation Solution
A transistor structure with a non-planar channel region, featuring a buried gate structure with perpendicular portions and dielectric layers, and a semiconductor layout structure with alternating buried gate structures, which increases saturation current and improves gate control ability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If memory cell size is reduced to achieve high integration and high density, then device size decreases, but gate control ability deteriorates and saturation current decreases
Solution Approach 1:
The patent transitions from a traditional planar gate structure to a three-dimensional U-shaped buried gate structure that extends vertically into the substrate. This dimensional change allows the gate to control the channel from multiple directions (top, bottom, and sidewalls), significantly improving gate control ability despite the reduced memory cell footprint. The U-shaped gate wraps around the channel region, providing enhanced electrostatic control in the vertical dimension while maintaining horizontal scaling.
Solution Approach 2:
The gate structure employs a U-shaped curved geometry rather than a straight linear configuration. This curvature allows the gate to envelop the channel region more effectively, with the rounded bottom portion of the U-shape providing omnidirectional control over the channel. The curved design maximizes the gate's control volume around the channel while minimizing the lateral space required, thus improving gate control ability without increasing device footprint.
2Volume of moving object
If memory cell size is reduced to achieve high integration and high density, then device size decreases, but saturation current decreases
Solution Approach 1:
The U-shaped buried gate structure extends vertically into the substrate, creating additional control volume around the channel. This three-dimensional configuration increases the effective gate-channel interaction area, enabling higher saturation current despite the reduced planar footprint of the memory cell. The vertical extension of the gate provides additional pathways for charge control, enhancing the transistor's current drive capability.
Solution Approach 2:
The patent merges the gate control function into a unified U-shaped structure that simultaneously controls the channel from the top, bottom, and sidewalls. This combined structure integrates multiple control surfaces into a single gate entity, maximizing the gate's influence over the channel region. The merged U-shaped design provides comprehensive electrostatic control that enhances carrier modulation and increases saturation current.
3Device complexity
If traditional straight buried gate structure is used, then device structure is simple, but gate control ability is insufficient
Solution Approach 1:
The patent introduces a vertical dimension to the gate structure by extending it downward into the substrate to form a U-shape. This adds complexity to the gate geometry, transforming it from a simple planar layer into a three-dimensional structure that wraps around the channel. The increased structural complexity enables superior gate control by providing electrostatic influence from multiple spatial directions.
Solution Approach 2:
The gate structure is designed with a U-shaped curved profile instead of a straight configuration. This curvature allows the gate to conformally surround the channel region, with the rounded bottom of the U-shape providing encirclement control. The curved geometry increases the gate's effective control volume and enhances electrostatic coupling with the channel, improving gate control ability at the cost of increased fabrication complexity.
Data Source
AI summary
The present disclosure provides a transistor structure and a semiconductor layout structure. The transistor structure includes an active region, a buried gate structure disposed in the active region, a plurality of first dielectric layers disposed over sidewalls of the buried gate structure, and a source/drain region disposed in the active region at two opposite sides of the buried gate structure. In some embodiments, the buried gate structure includes a first portion and a second portion perpendicular to the first portion. In some embodiments, the buried gate structure is separated from the source/drain region by the first dielectric layers as viewed in a top view.