Buried Gate Transistor for Compact OTP Memory
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Solution Overview
Problem
Current one-time programmable (OTP) memory devices occupy large surface areas and exhibit resistance dispersion issues due to uncontrollable oxide breakdown, leading to unsatisfactory performance.
Innovation Solution
The design incorporates a buried gate transistor with a capacitive element, where charges are focused to a specific location during programming, reducing the size of OTP memory cells and improving resistance control by using a buried channel portion and additional doping types to enhance charge concentration and insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional OTP memory structure is used, then memory function is achieved, but surface area occupied is large (several hundreds of square micrometers)
Solution Approach 1:
The patent introduces a buried channel portion extending in the vertical dimension beneath the gate electrode, transforming the traditional planar transistor structure into a three-dimensional configuration. This buried channel extends from the first lateral surface of the gate electrode to the second lateral surface, utilizing the depth dimension to increase effective channel area without increasing planar footprint, thereby reducing surface area while maintaining memory functionality
Solution Approach 2:
The patent segments the channel into a buried portion and separates it from the gate electrode using an insulator layer. This segmentation allows independent optimization of channel geometry and gate positioning, enabling precise control over charge distribution during oxide breakdown while minimizing the overall cell area
2Manufacturing precision
If oxide breakdown is allowed to occur naturally during programming, then memory state change is achieved, but resistance values show large dispersion between different memories
Solution Approach 1:
The patent applies local quality by creating a specifically doped buried channel portion with controlled dopant concentration and type. This localized modification of channel properties enables precise control over where and how oxide breakdown occurs, ensuring consistent resistance values across different memory cells while the rest of the structure remains relatively simple
3Area of moving object
If smaller OTP memory cells are designed, then surface area is reduced, but control over charge distribution during programming becomes difficult
Solution Approach 1:
By extending the channel vertically beneath the gate rather than expanding horizontally, the patent achieves area reduction while maintaining charge control. The buried channel's extension in the depth dimension provides sufficient channel length for charge accumulation without increasing the planar cell dimensions
Solution Approach 2:
The patent modifies the dopant concentration and type in the buried channel portion relative to the substrate, creating an optimized electrical profile that enhances charge carrier generation and confinement. This parameter change in the channel region improves charge focusing precision despite the reduced cell size
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in smaller OTP memory cells with reduced resistance dispersion, enabling more precise control over the oxide breakdown and improved performance by concentrating charges accurately, thus overcoming the size and dispersion issues of existing devices.
Implementation Method 1
During a step of cell programming to a second state (arbitrarily 1), the transistor sends a signal which enables the break down of the oxide, which makes it conductive with a given resistance which is relatively low
Data Source
AI summary
A one-time programmable memory cell includes a transistor coupled to a capacitor. The transistor includes at least one first conductive gate element arranged in at least one first trench formed in a semiconductor substrate, and at least one first channel portion buried in the substrate and extending at the level of at least a first lateral surface of the at least one first conductive gate element. The capacitor includes a capacitive element forming a memory. The at least one first channel portion is electrically coupled to an electrode of the capacitive element.