Buried Gate Transistor with Pyramidal Recess for Low Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high reliability and low resistance due to limitations in transistor design, particularly in the junction portion where the contact area between the impurity region and the contact pad is limited, leading to increased total resistance and potential defects from ion implantation processes.
Innovation Solution
The design incorporates a transistor with a buried gate and a junction portion featuring a recess with a pyramid-shaped bottom surface, an impurity region, and a contact pad, where the impurity region has a funnel shape and overlaps with the gate electrode, reducing contact resistance and preventing lattice damage, thereby improving device reliability and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional planar junction structure is used, then the manufacturing process is simple, but the contact area between impurity region and contact pad is limited, leading to high resistance
Solution Approach 1:
The patent applies curvature by forming the recess bottom surface with a pyramid shape instead of a planar structure. This curved/pyramidal surface increases the contact area between the impurity region and contact pad, thereby reducing contact resistance and improving device reliability without significantly complicating the manufacturing process
Solution Approach 2:
The patent transitions from a two-dimensional planar junction to a three-dimensional pyramidal recess structure. By adding vertical depth and creating a pyramidal geometry, the contact area is substantially increased while maintaining manufacturing feasibility through standard semiconductor processing techniques
2Reliability
If ion implantation is performed on a planar surface, then the process is straightforward, but lattice damage and defects occur
Solution Approach 1:
The patent performs preliminary action by forming the pyramidal recess structure before conducting ion implantation. This pre-formed geometric structure guides the ion implantation process, distributing ions more evenly and reducing lattice damage while improving contact area. The recess acts as a pre-prepared template that enhances subsequent manufacturing steps
3Reliability
If the contact area is increased to reduce resistance, then the device dimensions and complexity increase
Solution Approach 1:
The patent applies local quality by creating a pyramidal recess specifically at the contact region where increased surface area is needed, while leaving other parts of the device structure relatively simple. This localized geometric modification concentrates the complexity only where it provides benefit - at the contact interface between impurity region and contact pad
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly decreases the resistance of the source or drain transistor while enhancing device reliability by increasing the contact area and reducing electric field effects, leading to improved operation characteristics and reliability in semiconductor memory devices.
Implementation Method 1
a recess having a bottom surface protruded in a pyramid shape
Implementation Method 2
an impurity region formed in the substrate and under the recess
Data Source
AI summary
An electronic device includes a semiconductor memory unit that includes: a gate including at least a portion buried in a substrate; a junction portion formed in the substrate on both sides of the gate; and a memory element coupled with the junction portion on one side of the gate, wherein the junction portion includes: a recess having a bottom surface protruded in a pyramid shape; an impurity region formed in the substrate and under the recess; and a contact pad formed in the recess.