Buried Gate Transistor Contact Structures for Spreading Resistance
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Solution Overview
Problem
In highly integrated semiconductor devices with buried channel array transistors, the reduction of channel length to minimize spreading resistance is challenging due to increased depths of source/drain regions, which affects on-state currents and overall performance.
Innovation Solution
The semiconductor device incorporates a buried gate structure with a gate insulation layer, gate electrode, and capping layer, along with first and second impurity regions and buried contact structures that include metal silicide patterns, to reduce spreading resistance and enhance charge mobility by controlling mechanical stress on the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel length is reduced to minimize spreading resistance, then the on-state currents increase, but the source/drain region depths must be increased which complicates the manufacturing process
Solution Approach 1:
The source/drain structure is segmented into multiple regions with different doping concentrations and depths. The extended source/drain regions are divided into a first region with lower doping concentration and a second region with higher doping concentration, allowing each segment to be optimized independently for both electrical performance and manufacturability
Solution Approach 2:
Different regions of the source/drain structure are assigned different local properties: the extended source/drain regions have lower doping concentration to reduce resistance, while the contact regions have higher doping concentration for good contact. The gate structure also has localized doping regions that differ in concentration and depth from the channel region, allowing each local area to have optimal properties for its specific function
2Reliability
If the source/drain region depths are increased to reduce channel length, then the spreading resistance decreases, but the manufacturing complexity increases
Solution Approach 1:
The source/drain structure extends in multiple dimensions: laterally beyond the gate edges and vertically to different depths. The extended source/drain regions protrude from the substrate surface, creating a three-dimensional structure that reduces spreading resistance while maintaining manufacturability through controlled epitaxial growth and doping processes
3Productivity
If the channel length is reduced, then the transistor performance improves, but the source/drain region geometry becomes more complex
Solution Approach 1:
The source/drain structure exhibits dynamic geometry with regions that extend laterally beyond the gate edges and have varying depths. The extended source/drain regions create a stepped or tapered profile that adapts to the channel length reduction, allowing the structure to maintain optimal electrical characteristics while accommodating the compact transistor geometry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in high operating currents and charge mobility, improving the electrical characteristics of the transistor while maintaining low leakage currents, suitable for use in memory devices and other semiconductor applications.
Implementation Method 1
Each of the first and second buried contact structures include a metal silicide pattern and a metal pattern, and at least a portion of each of the first and second buried contact structures face to a sidewall of the buried gate structure
Implementation Method 2
The semiconductor device incorporates a buried gate structure with a gate insulation layer, gate electrode, and capping layer, along with first and second impurity regions and buried contact structures that include metal silicide patterns, to reduce spreading resistance and enhance charge mobility by controlling mechanical stress on the channel region
Data Source
AI summary
Semiconductor devices are provided including a substrate defining a gate trench. A buried gate structure is provided in the gate trench and at least fills the gate trench. The buried gate structure includes a gate insulation layer pattern, a gate electrode and a capping layer pattern. First and second impurity regions are provided at portions of the substrate adjacent to the buried gate structure, respectively. At least a portion of each of the first and second impurity regions face a sidewall of the buried gate structure. First and second buried contact structures are provided on the first and second impurity regions, respectively. Each of the first and second buried contact structures includes a metal silicide pattern and a metal pattern, and at least a portion of each of the first and second buried contact structures face to a sidewall of the buried gate structure.