Buried Gate Transistor Test Structure for Resistance Measurement
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Solution Overview
Problem
Conventional methods fail to precisely separate and measure the resistance components RT1 and RT2 along the sides of a buried gate in vertical transistor structures, which is crucial for characterizing electrostatic properties and minimizing total resistance.
Innovation Solution
A test structure with specific contact configurations and insulation layers allows for separate measurement of RT1 and RT2 by establishing distinct electrical conduction paths through a highly doped buried layer, enabling precise determination of these resistance components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional measurement methods (TLM, Hall effect, Van der Pauw, four point measurements) are used, then total resistance Ron can be measured, but the resistance components RT1 and RT2 along each side of the buried gate cannot be separated and precisely determined
Solution Approach 1:
The invention introduces a buried layer segmented into multiple regions (first buried region, second buried region, third buried region) with different doping concentrations. This segmentation allows separate measurement paths for RT1 and RT2, enabling precise determination of each resistance component along the sides of the buried gate while maintaining a manageable device structure.
2Ease of operation
If the sides of the buried gate are inclined or vertical, then conduction path is formed, but the resistance components RT1 and RT2 cannot be separately measured
Solution Approach 1:
The invention introduces a buried layer with specific doping concentrations as an intermediary structure between the substrate and the measurement contacts. This intermediary layer creates distinct measurement paths that allow separate determination of RT1 and RT2, making the measurement process feasible without modifying the basic transistor operation.
3Quantity of substance
If four contacts are used for conventional measurements, then total resistance can be obtained, but separate determination of RT1 and RT2 is not possible
Solution Approach 1:
The invention extends the measurement approach into the vertical dimension by introducing a buried layer at a specific depth in the substrate. This vertical dimensionality allows creation of separate measurement paths through different buried regions, enabling precise measurement of RT1 and RT2 without increasing the number of surface contacts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise separation and measurement of RT1 and RT2, improving the characterization of buried gate transistors and potentially reducing total resistance.
Implementation Method 1
A layer buried in the substrate, having a doping greater than or equal to 10^18 cm^-3... for establishing an electrical conduction path between the first transistor contact and the first test contact, passing through the buried layer and the first side of the gate
Implementation Method 2
The 2DEG is, in this case, typically confined by piezoelectric effect under the interface between the barrier layer 31 and the substrate 20
Data Source
AI summary
A test structure for a buried gate transistor includes a substrate, a first test contact located on one side of a first transistor contact, a second test contact located on one side of a second transistor contact, and a layer buried in the substrate, having a doping greater than or equal to 1018 cm−3, and having a face which is tangent to the buried part of the gate. A first insulation structure is disposed between the first test contact and the first transistor contact and a second insulation structure is disposed between the second test contact and the second transistor contact. The first and second test contacts each have an end connected to the buried layer.