Buried-Gate Trench Structure for Denser Wide-Bandgap Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing trench gate semiconductor devices face challenges in scaling to smaller geometries due to complexities in contact masking and contact etch geometries, which increase the pitch of unit cells and hinder increased cell density and power density.
Innovation Solution
The implementation of a buried gate contact within a gate trench of the semiconductor device, utilizing a multilayer gate structure with a gate polysilicon layer and a gate silicide layer, which is completely buried within the trench, reducing the need for contact masking and etch geometries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional trench gate structures are used with exposed gate contacts, then contact masking and etch geometries can be implemented, but cell pitch increases and cell density decreases
Solution Approach 1:
The gate contact is extracted from the surface and completely buried within the gate trench. The gate structure extends through the drift region and is terminated by a dielectric layer at the bottom of the trench, eliminating the need for surface contact masking and etch geometries. This extraction of the contact function to the trench interior directly reduces cell pitch while maintaining manufacturing precision.
2Ease of manufacture
If conventional gate structures are used, then manufacturing processes are simpler, but device performance and power density are limited
Solution Approach 1:
The gate structure transitions from a conventional planar configuration to a vertical three-dimensional structure extending through the drift region. The gate electrode, dielectric layer, and spacer layers are stacked vertically within the trench, creating a multi-layered architecture that increases power density while maintaining ease of manufacture through standard deposition and etching processes.
3Reliability
If gate trench geometry is optimized for performance, then device characteristics improve, but manufacturing complexity increases
Solution Approach 1:
The gate trench structure is segmented into distinct functional layers: the gate electrode for electrical control, the dielectric layer for insulation and termination, and the spacer layer for structural definition. This segmentation allows each layer to be optimized for its specific function while simplifying the overall manufacturing process through sequential deposition and etching steps.
Data Source
AI summary
Wide bandgap trench gate semiconductor devices are provided. In one example, a semiconductor device includes a wide bandgap semiconductor structure. The wide bandgap semiconductor structure includes a drift region of a first conductivity type and a well region of a second conductivity type. The semiconductor device includes a gate trench in the wide bandgap semiconductor structure. The gate trench extends through the well region into the drift region. The semiconductor device includes a buried gate structure in the gate trench. The buried gate structure includes a gate polysilicon layer and a gate silicide layer.