Buried Gate Trench Epitaxy for Lower Gate Resistance
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Solution Overview
Problem
As the width of trenches in semiconductor manufacturing decreases, it becomes challenging to fill gate structures, leading to increased resistance and decreased electrical performance of transistors due to narrower gate conductive layers.
Innovation Solution
A method involving providing a trench on a substrate, filling a gate structure in the bottom of the trench while exposing the sidewalls, growing an epitaxial layer on these sidewalls without closing the trench, and filling an isolation layer, which increases the width of the gate conductive layer and reduces its resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the trench width is reduced to improve integration level, then the level of integration is improved, but the gate conductive layer width is reduced leading to increased resistance
Solution Approach 1:
The patent introduces a vertical dimension by growing an epitaxial layer on the trench sidewalls. This adds height to the gate conductive layer without increasing its horizontal width, effectively transitioning from a 2D width-based resistance reduction approach to a 3D volume-based solution. The epitaxial growth on sidewalls creates additional conductive pathways in the vertical direction, compensating for the reduced horizontal width while maintaining high integration density.
2Productivity
If the trench width is reduced to improve integration level, then the level of integration is improved, but the gate conductive layer width is reduced leading to increased resistance
Solution Approach 1:
The patent introduces a vertical dimension by growing an epitaxial layer on the trench sidewalls. This adds height to the gate conductive layer without increasing its horizontal width, effectively transitioning from a 2D width-based resistance reduction approach to a 3D volume-based solution. The epitaxial growth on sidewalls creates additional conductive pathways in the vertical direction, compensating for the reduced horizontal width while maintaining high integration density.
3Productivity
If the trench width is reduced to improve integration level, then the level of integration is improved, but the resistance of gate conductive layer is increased
Solution Approach 1:
The patent introduces a vertical dimension by growing an epitaxial layer on the trench sidewalls. This adds height to the gate conductive layer without increasing its horizontal width, effectively transitioning from a 2D width-based resistance reduction approach to a 3D volume-based solution. The epitaxial growth on sidewalls creates additional conductive pathways in the vertical direction, compensating for the reduced horizontal width while maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical performance of buried gates by increasing the width of the gate conductive layer, thereby reducing its resistance without altering the level of integration, resulting in improved transistor performance.
Implementation Method 1
An epitaxial layer is grown on the exposed trench sidewalls with an epitaxial growth process, which does not close the trench
Data Source
AI summary
A method for manufacturing a buried gate and a method for manufacturing a semiconductor device are disclosed. The method for manufacturing the buried gate includes that: a trench is provided on an active region of a substrate; a gate structure is filled in a bottom of the trench, and a trench sidewall above the gate structure is exposed; an epitaxial layer is grown on the exposed trench sidewall with an epitaxial growth process, in which the epitaxial layer does not close the trench; and an isolation layer is filled in the trench.