Buried Gate Electrode Void Prevention via Trench Width Design
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Solution Overview
Problem
The generation of voids during the formation of buried gate electrodes in semiconductor devices, particularly due to narrow recess widths, which can lead to increased area occupation and reduced productivity in semiconductor memory devices.
Innovation Solution
A semiconductor device with a trench width 2.5 to 3 times wider than the buried gate, featuring a gate oxide layer, gate electrode, and a passivation layer pattern with spacers, and a method involving a hard mask layer etching process to prevent void formation and separate buried gate electrodes using self-aligned dry etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a narrow recess is used to form a buried gate electrode, then the area occupation is reduced, but voids are generated during the formation process
Solution Approach 1:
The patent changes the width parameter of the recess from narrow to wide (specifically, the recess width is set to be larger than the gate electrode width by a specific margin). This parameter change prevents void formation during the gate electrode filling process while still achieving area reduction through the vertical integration of the buried gate structure.
Solution Approach 2:
The patent transitions from a planar gate structure to a vertically integrated buried gate structure. By moving the gate electrode into the depth dimension (forming it in a recess below the surface), the device achieves area reduction on the surface plane while maintaining proper electrode formation without voids through the increased vertical space.
2Manufacturing precision
If a wide trench is used to prevent void formation, then manufacturing precision is improved, but area occupation increases
Solution Approach 1:
The patent resolves the area penalty by utilizing the vertical dimension. The wider recess is formed below the surface level, allowing the gate electrode to be embedded in the depth direction. This vertical integration frees up surface area for other device components while maintaining the wider recess geometry needed for void-free electrode formation.
Solution Approach 2:
The gate electrode is nested within the recess structure, which itself is embedded in the semiconductor substrate. This nested configuration allows the wider recess geometry to be contained within the device footprint without increasing the overall device area, as the structure extends vertically into the substrate rather than laterally on the surface.
3Productivity
If buried gate electrodes are formed closely together, then device density is improved, but shorts between bit lines and storage node contacts may occur
Solution Approach 1:
By forming the gate electrodes vertically in recesses below the surface, the patent creates natural vertical separation between adjacent device regions. This vertical stacking allows higher device density on the surface while the depth of the recesses provides physical isolation that prevents shorts between bit lines and storage node contacts, even when devices are closely spaced.
Solution Approach 2:
The patent segments the gate structure into distinct vertical regions within the recess, with the gate electrode separated from the surface level. This segmentation creates clear spatial separation between different functional regions (gate, source, drain, storage node), preventing electrical shorts while allowing close spacing of adjacent devices for high density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents void generation and improves semiconductor device properties by ensuring the trench width is sufficient for buried gate electrode formation, reducing area occupation and preventing shorts between bit lines and storage node contacts.
Implementation Method 1
forming a passivation layer pattern having a spacer shape on the sidewall of the trench and over the gate electrode
Implementation Method 2
performing a dry etch or a wet etching on the gate electrode material
Data Source
AI summary
A semiconductor device includes a semiconductor substrate including an active area defined by an device isolation region, a buried gate formed on both side walls of a trench formed in the semiconductor substrate, and a storage node contact which is buried between the buried gates, and is connected to the active region of a middle portion of the trench and the device isolation region.