Wave-Shaped Buried Gate Trenches for Sub-Critical Patterning
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Solution Overview
Problem
Existing photolithography processes face limitations in forming fine patterns with line widths below a critical dimension, necessitating new methods to improve process difficulty and secure process margins in semiconductor device fabrication.
Innovation Solution
A method involving the formation of a wave-shaped trench pattern and a buried gate structure, utilizing sacrificial spacers and hard mask patterns to etch and gap-fill trenches, which enhances the formation of fine patterns in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography process is used to form fine patterns, then existing manufacturing methods can be applied, but line widths below critical dimension cannot be formed
Solution Approach 1:
The patent segments the pattern formation process into multiple steps: forming sacrificial patterns, depositing spacers, selectively removing portions, and repeating the process. This multi-stage segmentation enables achievement of sub-critical-dimension line widths that cannot be obtained through single-step photolithography.
Solution Approach 2:
The patent transitions from planar 2D photolithography patterning to 3D spacer-based self-aligned patterning. By utilizing vertical spacer deposition and selective etching, the process achieves precision in the lateral dimension that exceeds the limitations of optical resolution.
2Manufacturing precision
If new methods are developed to form fine patterns below critical dimension, then line width precision is improved, but process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming sacrificial patterns and spacers before the final pattern definition. These preliminary structures serve as self-aligned masks and etch stop layers, simplifying subsequent processing steps and reducing the need for additional alignment-critical operations.
Solution Approach 2:
The spacer structures serve multiple functions simultaneously: they define pattern boundaries, act as etch masks, provide mechanical support, and enable self-aligned fabrication. This multi-functionality reduces the number of separate process steps needed compared to conventional photolithography approaches.
3Reliability
If conventional photolithography is used, then existing process margins are maintained, but process margin for fine patterns below critical dimension is insufficient
Solution Approach 1:
The patent incorporates buffer layers and sacrificial structures that provide process margin cushioning. These elements absorb variations in etch depth, spacer thickness, and alignment tolerances, ensuring that the final pattern dimensions remain within specifications even when process parameters vary.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces process complexity and secures process margins, enabling the fabrication of semiconductor devices with improved electrical characteristics and reduced short channel effects.
Implementation Method 1
forming a trench crossing the isolation layer and the active region in the first direction and disposed at a center of each active region by using the hard mask pattern as an etch barrier and etching the substrate
Data Source
AI summary
A semiconductor device includes an isolation layer defining a plurality of active regions in first and second directions; a plurality of trenches of a wave-shaped pattern extending in the first direction to cross the active regions and the isolation layer, the plurality of trenches being spaced apart from each other in the second direction; and a buried gate structure gap-filling the trenches, wherein the trenches correspond to the active regions and each active region is disposed one trench.