Buried Gate Work Function Adjusting Layer for Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Highly integrated semiconductor devices face reliability issues due to increased complexity, which affects their operating speed and power consumption, necessitating enhanced electrical characteristics to meet industry demands.
Innovation Solution
A semiconductor memory device is designed with buried gate lines comprising a conductive layer, a liner layer, and a work function adjusting layer, where the work function of the adjusting layer is less than that of the conductive and liner layers, and a method of manufacturing this device involves forming a trench in the substrate, depositing the layers, and diffusing a work function adjusting material to optimize electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high integration is implemented to increase operating speed and reduce power consumption, then device performance is improved, but reliability deteriorates
Solution Approach 1:
The patent applies local quality by introducing a work function adjusting layer with specific material composition and gradient structure at the interface between the gate line and substrate. This localized modification of material properties (work function, composition gradient) at the critical region directly addresses reliability issues without requiring changes to the overall high-integration device architecture, thus maintaining operating speed while improving reliability.
Solution Approach 2:
The patent employs composite materials by creating a multi-layer gate line structure consisting of a conductive layer, a liner layer, and a work function adjusting layer with varying material compositions. The work function adjusting layer itself may contain gradient composition or multiple sub-layers, forming a composite structure that optimizes both electrical performance and reliability in highly integrated devices.
2Ease of manufacture
If conventional gate line structures are used in highly integrated devices, then manufacturing is simpler, but electrical characteristics deteriorate
Solution Approach 1:
The patent applies segmentation by dividing the gate line into multiple functional layers: a conductive layer for electrical conduction, a liner layer for adhesion and protection, and a work function adjusting layer for electrical characteristic optimization. This segmented structure improves electrical characteristics while maintaining manufacturability through sequential deposition processes that are extensions of conventional semiconductor fabrication.
Solution Approach 2:
The patent employs parameter changes by modifying the work function of the gate line through the introduction of a work function adjusting layer with specific material composition and thickness. This changes the electrical parameters (threshold voltage, carrier concentration) of the device without fundamentally altering the manufacturing process flow, thus improving electrical characteristics while maintaining ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces gate-induced drain leakage current while maintaining high threshold voltage, enhancing the reliability and electrical characteristics of semiconductor memory devices.
Implementation Method 1
diffusing the first work function adjusting material from the source material layer into the preliminary first work function adjusting layer to form a first work function adjusting layer
Data Source
AI summary
Disclosed are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a device isolation layer defining active regions of a substrate, and gate lines buried in the substrate and extending across the active regions. Each of the gate lines includes a conductive layer, a liner layer disposed between and separating the conductive layer and the substrate, and a first work function adjusting layer disposed on the conductive layer and the liner layer. The first work function adjusting layer includes a first work function adjusting material. A work function of the first work function adjusting layer is less than those of the conductive layer and the liner layer.