Buried Gate Line Work-Function Tuning for Leakage Control
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Solution Overview
Problem
Semiconductor devices face challenges in achieving high reliability due to increased integration and demand for low power consumption, leading to fabrication failures and reduced electrical characteristics.
Innovation Solution
A semiconductor device fabrication method involving the formation of buried gate lines with a work-function control layer and conductive layer, where the work-function control layer has a lower work function in the upper portion to reduce gate-induced drain leakage current, while maintaining a higher work function in the lower portion for threshold voltage, using a barrier layer to facilitate diffusion of the work-function control element.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If semiconductor devices are highly integrated to increase speed and reduce power consumption, then operating speed and power efficiency are improved, but reliability deteriorates due to fabrication failures
Solution Approach 1:
The work-function control layer is designed with spatially varying properties: the lower portion has a first work function optimized for threshold voltage control, while the upper portion has a second work function optimized for reducing gate-induced drain leakage. This local differentiation allows simultaneous optimization of multiple electrical characteristics without compromising reliability
Solution Approach 2:
The gate structure is segmented into multiple functional layers: the work-function control layer is divided into lower and upper portions with different work functions, and a barrier layer is inserted between the work-function control layer and the conductive layer. This segmentation enables independent optimization of threshold voltage and leakage current characteristics
2Ease of manufacture
If a uniform work-function control layer is used in the gate line, then fabrication is simplified, but electrical characteristics deteriorate due to inability to control both threshold voltage and gate-induced drain leakage
Solution Approach 1:
Instead of using a uniform work-function control layer, the invention implements spatially varying work functions: the lower portion has a first work function for threshold voltage control, while the upper portion has a second work function for leakage reduction. This resolves the contradiction by making different parts of the same layer serve different electrical functions
Solution Approach 2:
The work-function control layer is segmented into lower and upper portions with distinct work function values, achieved through selective deposition or doping processes. This segmentation enables precise control of both threshold voltage and gate-induced drain leakage characteristics while maintaining a relatively simple overall fabrication process
3Reliability
If the work-function control layer has high work function throughout, then threshold voltage is maintained, but gate-induced drain leakage current increases
Solution Approach 1:
The work-function control layer exhibits local quality variation: the lower portion maintains high work function for threshold voltage stability, while the upper portion has reduced work function to minimize gate-induced drain leakage. This spatial differentiation resolves the contradiction by assigning different functional priorities to different regions of the gate structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances electrical characteristics by reducing gate-induced drain leakage current and maintaining a higher threshold voltage, thereby improving the reliability and performance of semiconductor devices.
Implementation Method 1
diffusing the work-function control element from the source layer into an upper portion of the work-function control layer
Data Source
AI summary
A semiconductor device, and a method of fabricating the semiconductor device including forming on a substrate a device isolation layer defining a plurality of active regions; and forming a plurality of gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming on the substrate a trench that intersects the active regions; forming a work-function control layer on a sidewall and a bottom surface of the trench; forming a conductive layer on the work-function control layer; sequentially forming a barrier layer and a source layer on the work-function control layer and the conductive layer, the source layer including a work-function control element; and diffusing the work-function control element from the source layer into an upper portion of the work-function control layer.


