Buried Ground Rail ROM Bitcell Architecture
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Solution Overview
Problem
Conventional ROM bitcell designs are inefficient in power, performance, and area due to fewer programming layers, which limits their ability to rewrite data without reprogramming all layers, and struggles with RC issues in bitlines and wordlines.
Innovation Solution
The implementation of a buried power rail architecture in ROM bitcell fabrication, using complementary FET technology, which couples ROM bitcells to ground (VSS or GND) and reduces bitline capacitance, enabling 1CPP wide ROM bitcell architectures for improved performance and area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional ROM bitcell designs use fewer programming layers for cost efficiency, then manufacturing cost is reduced, but power efficiency and performance deteriorate
Solution Approach 1:
The patent introduces a buried ground rail positioned beneath the bitline in the substrate, creating a new spatial dimension for ground connection. This buried rail architecture separates the ground path from the conventional frontside routing, enabling improved power efficiency without increasing programming layer complexity or manufacturing cost.
2Ease of manufacture
If conventional ROM bitcell designs use fewer programming layers, then manufacturing cost is reduced, but area efficiency deteriorates
Solution Approach 1:
By positioning the ground rail in the substrate beneath the bitline, the patent utilizes the vertical dimension to improve area efficiency. This buried configuration allows for more compact bitcell layouts without adding lateral space requirements, maintaining cost efficiency while reducing area.
3Ease of manufacture
If conventional ROM bitcell designs use fewer programming layers, then manufacturing cost is reduced, but RC issues in bitlines and wordlines worsen
Solution Approach 1:
The buried ground rail creates a dedicated ground path beneath the bitline, separating it from frontside signal routing. This dimensional separation reduces capacitive coupling and resistance between signal lines and ground, thereby reducing RC issues without affecting manufacturing cost or programming layer structure.
4Use of energy by moving object
If buried power rail architecture is implemented, then power efficiency is improved, but device complexity increases
Solution Approach 1:
The substrate itself serves as the hosting structure for the buried ground rail, utilizing the existing substrate material and fabrication capabilities. This self-service approach allows the ground rail to be integrated without requiring additional complex processing steps or external components, thereby improving power efficiency while minimizing increases in device complexity.
Data Source
AI summary
Various implementations described herein are related to a device with a backside power network. The backside power network may have a buried power rail that is coupled to ground. The device may have a read-only memory (ROM) cell that is coupled between at least one bitline and the buried power rail, and the ROM cell may be coupled to ground by way of the buried power rail.