Buried Guard Ring Structure for Radiation-Hardened CMOS
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Solution Overview
Problem
The existing technologies for producing radiation-hardened integrated circuits (RHICs) face financial constraints and technological disparities, leading to limited capabilities compared to commercial ICs, with the COTS approach failing to provide reliable and cost-effective solutions for radiation-exposed environments.
Innovation Solution
The development of semiconductor devices with specialized structures such as parasitic isolation devices and buried guard rings, which can be integrated into conventional CMOS fabrication processes to reduce radiation-induced degradation, including Total Ionizing Dose, Single Event Latch-up, and Single Event Upset effects, without impacting commercial baseline electrical parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS fabrication processes are used for commercial ICs, then manufacturing cost is reduced and productivity is improved, but radiation hardness is insufficient leading to device failure in radiation environments
Solution Approach 1:
The patent applies preliminary action by forming a buried guard ring structure during the early stages of CMOS fabrication, specifically by implanting ions at a first energy level to create a shallow buried layer, then implanting at a second higher energy level to form a deeper buried layer. This preliminary structuring prevents radiation-induced latch-up before devices are exposed to radiation environments, resolving the contradiction between maintaining simple fabrication processes and achieving radiation hardness.
2Reliability
If dedicated leading-edge manufacturing facilities are deployed for radiation-hardened ICs, then radiation hardness is improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent applies universality by designing a buried guard ring structure that can be integrated into standard CMOS fabrication processes already used for commercial ICs. The multi-energy ion implantation technique allows the same fabrication facility to produce both commercial and radiation-hardened devices using the same baseline process, eliminating the need for dedicated expensive facilities while maintaining radiation hardness.
3Ease of manufacture
If COTS approach is used to procure commercial ICs for radiation environments, then cost is reduced, but reliability deteriorates due to radiation-induced latch-up and soft errors
Solution Approach 1:
The patent applies local quality by implementing a specific buried guard ring structure at critical locations within the CMOS device architecture. The structure uses selectively doped regions with different conductivity types (n-type and p-type layers) positioned strategically to prevent latch-up at specific vulnerability points, thereby providing localized radiation protection while maintaining overall device functionality and cost-effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These structures significantly reduce the sensitivity of integrated circuits to ionizing radiation, preventing latch-up and soft errors, thereby enhancing radiation hardening properties while maintaining circuit performance and size, enabling the creation of cost-effective RHICs for military and aerospace applications.
Implementation Method 1
collecting the charge onto a buried layer formed within the substrate region
Implementation Method 2
shunting the collected charge from the buried layer to a surface terminal through a conductive path comprising a conductive region
Implementation Method 3
exposing an operating semiconductor device to ionizing radiation, and thereby generate charge within a substrate region
Data Source
AI summary
Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.