Buried Insulating Layer for Electrostatic Control in Fully Depleted Devices
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Solution Overview
Problem
Current semiconductor devices face challenges in scaling down channel thickness and maintaining electrostatic control as they approach next technology nodes, leading to issues like the floating body effect and threshold voltage roll-off, especially in partially depleted SOI devices.
Innovation Solution
The introduction of a buried insulating material layer with a thickness of about 10-20 nm, surrounded by an active region and bordering the channel region, which allows for improved electrostatic control and reduced interference between source and drain electric fields, enabling the formation of fully depleted semiconductor devices without the need for doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel thickness is scaled down to continue miniaturization, then device density and integration are improved, but electrostatic control deteriorates and threshold voltage roll-off occurs
Solution Approach 1:
The patent introduces a buried insulating layer at a specific depth beneath the channel region, transitioning from two-dimensional planar control to three-dimensional spatial control. This vertical dimension allows electrostatic control without increasing lateral dimensions, enabling continued device scaling while maintaining reliable threshold voltage control through the additional control electrode positioned in the depth dimension.
2Loss of energy
If conventional SOI structures are used, then parasitic capacitance is reduced, but floating body effect and threshold voltage roll-off occur
Solution Approach 1:
The buried insulating layer acts as an intermediary element between the substrate and the channel region. It provides electrical isolation that maintains the low parasitic capacitance benefit of SOI structures while preventing the floating body effect through proper potential control, thus mediating between the conflicting requirements of low capacitance and stable threshold voltage.
Solution Approach 2:
The patent changes the electrical parameters of the substrate interface by introducing the buried insulating layer with specific material properties and thickness. This parameter change transforms the substrate from a potentially harmful floating body to a controlled element, eliminating threshold voltage roll-off while preserving the low parasitic capacitance characteristic.
3Reliability
If doping is used to control threshold voltage, then switching characteristics are improved, but device complexity and fabrication precision requirements increase
Solution Approach 1:
The patent replaces the chemical/doping-based threshold voltage control mechanism with an electrical/electrostatic control mechanism using the buried insulating layer and control electrode. This substitution eliminates the need for precise doping processes and thermal annealing steps, reducing fabrication complexity while maintaining reliable switching characteristics through voltage control.
Data Source
AI summary
A semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and a buried insulating material region disposed in the active region under the gate structure. The buried insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth of the active region. The source/drain regions have a depth greater than a top surface of the buried insulating material region.