Buried-Insulator Nanosheet SRAM for Read Margin Without Assist Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
FinFET devices experience short channel effects such as leakage currents and reduced transistor performance due to reduced gate length, necessitating the use of read assist circuits in SRAM devices to improve read performance.
Innovation Solution
The implementation of a partial buried insulator (BI) nano-sheet device in SRAM bitcells, where a BI layer is formed beneath a source or drain region and nano-sheets separate the source and drain regions, enhancing gate controllability and eliminating the need for read assist circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the channel length of MOSFET is reduced to make devices smaller, then device size is reduced, but transistor performance deteriorates due to reduced control over the channel region
Solution Approach 1:
The patent transitions from planar 2D channel structure to a 3D FinFET structure with vertical fins extending from the substrate. This dimensional change allows the gate to control the channel from multiple surfaces (top, bottom, and sidewalls), significantly improving gate control effectiveness while maintaining reduced device footprint.
Solution Approach 2:
The channel region is segmented into multiple fins rather than a single planar channel. Each fin acts as an independent current path controlled by the gate, allowing better overall control while maintaining compact device size. The segmented fin structure enables superior electrostatic control compared to a single large channel.
2Volume of moving object
If the gate length is reduced in FinFET to further miniaturize devices, then device size is reduced, but short channel effects such as leakage currents and threshold voltage variations increase
Solution Approach 1:
By extending the channel vertically into fins, the gate gains control over the channel from multiple dimensions (top, bottom, and sidewalls). This multi-surface control compensates for the reduced gate length by increasing the effective gate control area, thereby suppressing short channel effects like leakage currents and threshold voltage variations even in miniaturized devices.
Solution Approach 2:
The patent employs a composite structure combining silicon fins with high-k dielectric materials and metal gates. The high-k dielectric provides superior electrical insulation with thinner layers, reducing leakage currents, while the metal gate offers better electrostatic control. This composite material approach effectively mitigates short channel effects in scaled devices.
3Reliability
If read assist circuits are added to improve read performance in SRAM devices, then read performance is improved, but device complexity and area increase
Solution Approach 1:
The FinFET structure provides self-service by inherently delivering improved read performance through its superior gate control and higher drive current capability. The enhanced transistor performance from the 3D fin structure naturally improves SRAM read margins without requiring external read assist circuits, allowing the device to serve its own performance needs.
Solution Approach 2:
The patent extracts and eliminates the need for read assist circuits by incorporating the necessary performance enhancement directly into the FinFET transistor structure itself. The improved gate control and current drive from the fin structure provide sufficient read performance margin, allowing the removal of additional complex read assist circuitry.
Data Source
AI summary
Devices and methods are described herein that obviate the need for a read assist circuit. In one example, a semiconductor device includes a source region and a drain region formed above a substrate. A buried insulator (BI) layer is formed beneath either the source region or the drain region. A first nano-sheet is formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer. The BI layer reduces current flow through the first nano-sheet.