Buried Interconnect Layout for BEOL Congestion Relief
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Solution Overview
Problem
The semiconductor industry faces congestion issues in the Back-End-Of-Line (BEOL) metal stack due to increasing device density, leading to sub-optimal power, performance, and density solutions, as traditional 2D scaling methods fail to maintain pace with device miniaturization, resulting in parasitic resistance and capacitance challenges.
Innovation Solution
A method involving the formation of interconnects within the bulk semiconductor material, where a first wiring structure is formed within the substrate, followed by epitaxial growth of active semiconductor material and the creation of active devices, with a second wiring structure formed above these devices, allowing for efficient power and signal routing and reducing congestion by leveraging the vertical axis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 2D scaling is used to increase device density, then device miniaturization is achieved, but BEOL metal stack congestion increases and parasitic resistance and capacitance worsen
Solution Approach 1:
The patent applies dimensionality change by moving interconnect levels from the traditional 2D plane (above active devices) into the 3D bulk substrate. Multiple wiring structures are formed at different depths within the substrate, transforming the interconnect architecture from a planar layout to a volumetric three-dimensional structure. This allows power and signal routing to occur below the active device layer, effectively adding vertical dimensionality to the interconnect space and relieving BEOL congestion.
2Quantity of substance
If more interconnect levels are added above active devices, then connectivity density increases, but parasitic resistance and capacitance increase
Solution Approach 1:
The patent reduces parasitic effects by routing interconnects through the bulk substrate rather than through thin dielectric layers above devices. The three-dimensional wiring structures are embedded in the substrate volume, allowing longer interconnect paths with controlled impedance and reduced capacitive coupling to adjacent lines. This spatial separation in the vertical dimension decreases parasitic capacitance compared to traditional stacked BEOL architectures.
3Device complexity
If bulk substrate space is utilized for wiring structures, then interconnect congestion is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent employs preliminary action by forming the three-dimensional wiring structures within the bulk substrate before the active devices are fabricated. The substrate is pre-patterned with wiring channels and conductive structures at designated depths, creating a prepared interconnect framework. Subsequently, active devices are formed on the surface and connected to this pre-existing sub-surface wiring network, separating the interconnect fabrication timeline from the device fabrication timeline and enabling independent optimization of each.
Solution Approach 2:
The manufacturing process is segmented into distinct stages: substrate preparation with embedded wiring structures, followed by active device formation, and finally interconnection between the two. The wiring structures themselves are segmented into multiple discrete layers at different depths within the substrate, each formed through separate patterning and filling operations. This segmentation allows each manufacturing step to be independently controlled and optimized.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces congestion in the top-side interconnects, enables efficient power delivery, and enhances chip performance and density by utilizing the bulk substrate's unused space, thereby addressing scaling limitations and improving power and performance.
Implementation Method 1
epitaxially growing active semiconductor material over the first wiring structure
Data Source
AI summary
An additional set of interconnects is created in bulk material, allowing connections to active devices to be made from both above and below. The interconnects below the active devices can form a power distribution network, and the interconnects above the active devices can form a signaling network. Various accommodations can be made to suit different applications, such as encapsulating buried elements, using sacrificial material, and replacing the bulk material with a dielectric. Epitaxial material can be used throughout the formation process, allowing for the creation of a monolithic substrate.