Buried Interconnect Layout for BEOL Congestion Relief
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Solution Overview
Problem
The semiconductor industry faces challenges in maintaining node-to-node improvement in power-performance-area-cost (PPAC) due to congestion issues in the Back-End-Of-Line (BEOL) metal stack, which is exacerbated by the increasing density of active devices and parasitic resistance and capacitance.
Innovation Solution
A method of fabrication that involves forming a first wiring structure within the bulk semiconductor material, epitaxially growing active semiconductor material over it, forming active devices, and creating a second wiring structure above the active devices, thereby leveraging the vertical axis for additional interconnect levels and reducing congestion in the BEOL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional interconnect levels are added to the BEOL metal stack to maintain connectivity as devices scale, then device density increases, but parasitic resistance and capacitance increase drastically
Solution Approach 1:
The patent moves interconnect levels from the traditional planar BEOL space above active devices to the vertical dimension by forming wiring structures within the bulk substrate. This dimensional transition allows interconnects to occupy the unused bulk space below active devices, thereby increasing device density on the surface while reducing parasitic effects through optimized current paths and reduced metal stack congestion.
2Quantity of substance
If the density of active devices on the substrate surface is increased to follow Moore's law, then circuit functionality improves, but congestion issues in the BEOL metal stack worsen
Solution Approach 1:
The patent relocates wiring structures from the congested planar BEOL space to the vertical bulk substrate dimension. By forming openings and filling them with conductive material within the bulk substrate, the patent creates interconnect levels that do not compete for space with the BEOL metal stack above active devices, thereby supporting higher device densities without exacerbating BEOL congestion.
Solution Approach 2:
The patent embeds wiring structures within the bulk substrate, effectively nesting interconnect levels inside the substrate volume below active devices. This nesting approach allows multiple interconnect layers to coexist within the substrate without interfering with the BEOL metal stack, thereby reducing congestion while supporting increased device density.
3Adaptability or versatility
If interconnect levels are moved below active devices to reduce BEOL congestion, then routing capacity improves, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming openings in the bulk substrate and filling them with conductive material before fabricating active devices on the surface. This sequential approach, where wiring structures are pre-formed in the bulk substrate, simplifies subsequent device fabrication and reduces overall manufacturing complexity despite the innovative routing capacity provided by subsurface interconnects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces congestion in the BEOL, enhances power delivery, and improves performance and density by utilizing the bulk substrate's unused space and volume, thereby maintaining PPAC improvements.
Implementation Method 1
epitaxially growing active semiconductor material over the first wiring structure
Data Source
AI summary
An additional set of interconnects is created in bulk material, allowing connections to active devices to be made from both above and below. The interconnects below the active devices can form a power distribution network, and the interconnects above the active devices can form a signaling network. Various accommodations can be made to suit different applications, such as encapsulating buried elements, using sacrificial material, and replacing the bulk material with a dielectric. Epitaxial material can be used throughout the formation process, allowing for the creation of a monolithic substrate.