Buried Interconnect Layout for Low-Resistance BPR Contacts
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Solution Overview
Problem
The formation of low resistance connections between local interconnects and buried power rails (BPRs) in integrated circuits is challenging due to increased sensitivity to stochastic errors in the integration process, such as overlay errors and over etching, which reduces process margins.
Innovation Solution
A method for forming a semiconductor device that involves creating a trench for a buried interconnect structure between fin structures, lining the trench with a dielectric layer, and selectively etching contact openings to facilitate the formation of local interconnects that can extend laterally to interface with the buried interconnect structure, thereby reducing isolation margins and improving contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the contact interface between the PV and the BPR is enlarged to reduce connection resistance, then the line resistance is reduced, but the spacing between local interconnects is reduced which reduces process margins and increases sensitivity to stochastic errors
Solution Approach 1:
The patent transitions from a planar contact interface to a three-dimensional contact structure by forming contact openings that extend vertically into the substrate and laterally along the BPR. This dimensional change allows the contact interface area to be increased without proportionally increasing the footprint spacing between adjacent contacts, thereby reducing connection resistance while maintaining adequate process margins.
Solution Approach 2:
The contact opening structure is formed nested within the isolation layer structure, with the contact opening extending through the isolation layer to reach the BPR. This nested configuration allows the contact interface to be embedded within the existing structure hierarchy, maximizing the contact area along the BPR length while maintaining compact spacing between adjacent local interconnects.
2Reliability
If the PV size is increased to reduce connection resistance, then the contact interface area is increased, but the spacing between adjacent local interconnects is reduced which increases sensitivity to overlay errors and over etching
Solution Approach 1:
The contact structure is segmented into distinct regions: a vertical portion extending through the isolation layer and a lateral portion extending along the BPR. This segmentation allows the contact interface to be divided into multiple contact points along the BPR length, increasing the total contact area while distributing the structural complexity across separate formation steps, thereby reducing sensitivity to integration errors.
3Productivity
If the local interconnect spacing is reduced to increase density, then the routing congestion is reduced, but the process margins for PV and local interconnect formation are reduced which increases sensitivity to stochastic errors
Solution Approach 1:
The isolation layer structure is differentiated into regions with different properties: regions with contact openings that extend through the isolation layer to provide enlarged contact interfaces, and regions without contact openings that maintain standard isolation. This local differentiation allows increased interconnect density in areas with enlarged contacts while preserving adequate process margins in areas with standard spacing.
Data Source
AI summary
A method for forming a semiconductor device includes forming a trench for a buried interconnect structure between first and second fin structures and lining the trench with a dielectric layer. The method also includes etching a contact opening in a first portion of the dielectric layer adjacent a first region of the first fin structure while masking the second portion of the dielectric layer adjacent a second region of the second fin structure directly opposite the first region. The method also includes forming a local interconnect trench extending between the first and second regions, where the second portion of the dielectric layer partitions the local interconnect trench into first and second trench portions. The method also includes forming first and second local interconnects in the first and second trench portions. The first and second local interconnects are separated by the second portion of the dielectric layer.