Buried Source/Drain Interconnect Layout With Gate Short Protection
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices necessitates finer patterns and three-dimensional channel structures to overcome limitations in planar metal oxide semiconductor FETs, requiring improved integration and operating characteristics.
Innovation Solution
A semiconductor device design featuring an active region with recessed source/drain regions, protective layers, and a buried interconnection line below these regions, connected to the source/drain regions, allowing for self-alignment and enhanced integration while preventing electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If finer patterns and three-dimensional channel structures are implemented to increase integration degree, then device performance and speed improve, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent applies preliminary action by forming protective layers (first protective layers covering lower surfaces of gate structures and second protective layers below channel layers) before forming the buried interconnection line. This pre-positioned protective layer structure guides the subsequent formation of the buried interconnection line through self-alignment, simplifying the manufacturing process despite the complex three-dimensional device structure
Solution Approach 2:
The protective layers serve as intermediary elements that mediate between the gate structures/channel layers and the buried interconnection line. These intermediary layers enable precise positioning and electrical isolation without requiring complex alignment processes, thus reducing manufacturing complexity while maintaining high device performance
2Reliability
If buried interconnection line is placed below source/drain regions for better integration, then electrical connection stability improves, but risk of electrical short between interconnection line and gate structures increases
Solution Approach 1:
The first protective layers positioned between the device isolation layer and lower surfaces of gate structures serve as intermediary insulating barriers. These intermediary layers physically separate the buried interconnection line from the gate structures, preventing electrical shorts while maintaining stable electrical connections to the source/drain regions
Solution Approach 2:
The patent resolves the electrical short risk by transitioning to a three-dimensional arrangement where protective layers are positioned at different vertical levels (depths) relative to the buried interconnection line and gate structures. This dimensional separation in the vertical direction provides effective electrical isolation while maintaining planar integration
3Manufacturing precision
If protective layers are added to prevent electrical shorts and enable self-alignment, then manufacturing precision improves, but device structure complexity increases
Solution Approach 1:
The protective layers are designed to serve dual functions: they provide electrical isolation and simultaneously act as self-alignment guides for forming the buried interconnection line. The self-service nature of these layers, where the same structural elements perform multiple functions, reduces the need for additional complex alignment structures and processes
Data Source
AI summary
A semiconductor device includes an active region extending in a first direction; a device isolation layer on side surfaces of the active region and defining the active region; a gate structure intersecting the active region on the active region and extending in a second direction; source/drain regions in regions in which the active region is recessed, on both sides of the gate structure; first protective layers between the device isolation layer and the gate structure; and a buried interconnection line below the source/drain regions and connected to one of the source/drain regions through an upper surface of the buried interconnection line.