Buried Interconnect Structures for High Density ICs
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Solution Overview
Problem
As design rules in semiconductor devices decrease, the probability of contact between plugs and interconnections increases, leading to poor electrical characteristics due to complex configurations, which degrade the performance of semiconductor devices and modules.
Innovation Solution
The integration of trench isolation regions and recesses in semiconductor substrates with insulating capping patterns and interconnect insulating layers, along with orthogonal electrical interconnects, reduces the contact probability between plugs and interconnections by creating longer distances and using sidewall spacers to prevent physical contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If design rules are decreased to increase interconnect density, then productivity is improved, but the probability of contact between plugs and interconnections increases leading to worsened reliability
Solution Approach 1:
The patent introduces a vertical dimension by forming a recess into the substrate and placing an insulating layer within it. This third-dimensional approach separates the plug and interconnection in the vertical direction while maintaining their horizontal proximity, thereby increasing interconnect density without causing electrical contact
Solution Approach 2:
An insulating layer is introduced as an intermediary between the plug and the interconnection. This intermediate layer physically separates the two conductive elements, preventing direct electrical contact while allowing them to remain in close proximity for efficient signal transmission
2Reliability
If complicated configuration is used to reduce contact probability, then reliability is improved, but device complexity increases leading to worsened ease of manufacture
Solution Approach 1:
The structure is segmented into distinct functional layers: the substrate, the recess formed therein, the insulating layer within the recess, and the interconnection above. This segmentation simplifies the overall configuration by clearly separating the plug and interconnection with a dedicated insulating structure, making the manufacturing process more straightforward
3Productivity
If distance between plug and interconnection is decreased to increase density, then productivity is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
By utilizing the vertical dimension through the recess structure, the patent achieves separation of plug and interconnection without reducing horizontal distance. This allows maintaining larger process margins in the horizontal plane while still achieving high density through vertical stacking
Data Source
AI summary
Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer. A second electrical interconnect is also provided, which extends on: (i) an upper surface of the first trench isolation region, (ii) the electrically insulating capping pattern; and (iii) the sidewall of the recess. The first and second electrical interconnects extend across the semiconductor substrate in first and second orthogonal directions, respectively.


