Buried Interconnect PCB Structure for Low-Cost HBM Chip Mounting
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Solution Overview
Problem
Existing techniques for connecting semiconductor chips to circuit boards, such as silicon bridges and interposers, are limited by high costs and complex assembly processes, which hinder the commercialization of high bandwidth memory (HBM) connections and die-splitting techniques.
Innovation Solution
A printed circuit board design that includes a first build-up insulating layer with a buried interconnect structure, an adhesive layer, and a metal bump with a via portion and protrusion, allowing for direct mounting of semiconductor chips without requiring expensive processes like CMP, and providing excellent flatness and improved packaging yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon bridge or silicon interposer techniques are used to connect dies with fine circuit line width, then connection capability is improved, but manufacturing cost increases and process complexity increases
Solution Approach 1:
The patent replaces expensive silicon interposers with organic resin-based build-up layers that can be manufactured using standard PCB processes. The interconnect structure is formed through sequential lamination of prepreg and copper foil, eliminating the need for costly silicon material and CMP processes while achieving the required fine pitch interconnections.
Solution Approach 2:
The patent substitutes mechanical polishing (CMP) with a lamination-based approach. Instead of using CMP to flatten surfaces and form vias, the invention uses layered prepreg and copper foil structures with standard drilling and plating processes, replacing complex mechanical systems with simpler, more cost-effective manufacturing methods.
2Reliability
If silicon bridge or silicon interposer techniques are used to connect dies with fine circuit line width, then connection capability is improved, but process complexity increases
Solution Approach 1:
The patent divides the interconnect structure into multiple discrete layers of preprep and copper foil, each serving a specific function. The build-up process is segmented into sequential steps of lamination, drilling, and plating, allowing each layer to be manufactured and controlled independently, thereby reducing overall process complexity.
Solution Approach 2:
The patent uses standard PCB manufacturing processes (lamination, drilling, plating) to achieve multiple functions: forming interconnect layers, creating vias, and establishing electrical connections. This multi-functionality eliminates the need for specialized silicon processing equipment and procedures, simplifying the overall manufacturing process.
3Manufacturing precision
If encapsulation on front surface with CMP process is used to achieve flatness, then surface flatness is improved, but manufacturing cost increases
Solution Approach 1:
The patent incorporates flatness control into the lamination process itself. By carefully selecting and stacking prepreg materials with appropriate thicknesses and physical properties, the desired surface flatness is achieved during the build-up process, eliminating the need for subsequent costly CMP operations.
Solution Approach 2:
The patent replaces expensive CMP processing with a cost-effective lamination approach using standard PCB materials. The flatness is achieved through the inherent properties of the preprep and lamination process, avoiding the need for expensive CMP equipment and consumables.
Data Source
AI summary
A printed circuit board includes a first build-up insulating layer; an interconnect structure buried in an upper side of the first build-up insulating layer and including one or more insulating layers, one or more wiring layers, and one or more via layers; an adhesive disposed between an upper surface of the first build-up insulating layer and an upper surface of the interconnect structure, and having an upper surface exposed from the upper surface of the first build-up insulating layer; and a metal bump including a via portion penetrating the adhesive and a protrusion protruding to the upper surface of the adhesive.


