Buried Interconnects for Semiconductor Circuit Density
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Solution Overview
Problem
Current semiconductor circuits face challenges in achieving high circuit density while minimizing area, as existing buried interconnect structures do not fully optimize electrical routing and transistor placement.
Innovation Solution
A semiconductor circuit design featuring a Front End of Line (FEOL) with transistors having a buried interconnect connected to gate electrodes from below, along with a Middle End of Line (MOL) local interconnects that reduce routing area and footprint by allowing lateral contact alignment with metal layers, and a power interconnect for efficient power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional buried interconnect structures are used, then electrical routing is provided, but circuit density is limited and footprint is larger
Solution Approach 1:
The patent transitions from planar routing to three-dimensional routing by placing interconnects at multiple vertical levels (first buried interconnect at first level, second buried interconnect at second level). This vertical stacking enables higher circuit density without increasing lateral footprint, as signals can route through the depth dimension rather than requiring additional horizontal space.
Solution Approach 2:
The patent implements nested interconnect structures where shallower interconnects are positioned within vertical trenches that extend through deeper regions. This nesting allows multiple interconnect layers to occupy overlapping lateral footprints at different depths, maximizing space utilization and achieving high density without proportionally increasing the device area.
2Productivity
If more interconnect layers are added to increase density, then routing capacity improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the interconnect structure into discrete, manageable segments: first buried interconnects at a first vertical level, second buried interconnects at a second vertical level, with each layer independently formed and connected through localized vertical trenches. This segmentation allows systematic manufacturing of complex multi-layer structures by breaking down the process into repeatable unit operations.
Solution Approach 2:
The patent performs preliminary formation of isolation regions and first buried interconnects before creating vertical trenches for second buried interconnects. This sequential preparation ensures that each manufacturing step builds upon a ready substrate, reducing complexity by eliminating the need for simultaneous multi-step processing and allowing quality verification at intermediate stages.
Data Source
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AI summary
A semiconductor circuit (10) is disclosed, comprising a Front End of Line comprising a plurality of transistors, each of which having a source region (110), a drain region (120) and a gate region (100) arranged between the source region and the drain region and comprising a gate electrode (101). The semiconductor circuit also comprises a buried interconnect (130) that is arranged in the FEOL (160) and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. By using a buried interconnect the routing of the circuit may be facilitated.