Buried Die Interconnect Layout to Replace Through-Substrate Vias
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Solution Overview
Problem
Conventional approaches for providing external contacts to semiconductor devices using through-substrate vias cause mechanical stresses and increase manufacturing costs, leading to unpredictable device performance variations.
Innovation Solution
Employing buried electrical interconnects that run parallel to the upper and lower surfaces of a semiconductor die, reducing the need for interconnections through the substrate and allowing edge contacts, which are formed using conductive materials like tungsten, copper, or nickel, surrounded by dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-substrate vias are used for external contacts, then electrical connections are established, but mechanical stresses increase and manufacturing costs increase
Solution Approach 1:
The patent transitions from vertical through-substrate vias to lateral buried interconnects that extend horizontally from the device region to the die edge. This dimensional change eliminates the need for vertical penetration through the substrate, thereby reducing mechanical stresses while maintaining electrical connectivity.
Solution Approach 2:
The invention extracts the interconnect function from the substrate thickness direction (vertical) and relocates it to the lateral direction within a buried region. This separation allows the substrate to maintain its structural integrity without the stress-concentrating effect of through-substrate vias.
2Reliability
If through-substrate vias are used for external contacts, then electrical connections are established, but manufacturing costs increase
Solution Approach 1:
By routing interconnects laterally within a buried region rather than vertically through the substrate, the patent simplifies the manufacturing process. This approach eliminates complex via formation steps, reduces material waste, and lowers overall manufacturing costs while maintaining reliable electrical connections.
3Ease of operation
If through-substrate vias are used, then external contacts are provided, but device performance variations become unpredictable
Solution Approach 1:
The patent extracts the interconnect structure from the substrate bulk and relocates it to a controlled buried region near the die edge. This separation isolates the interconnect formation process from substrate variations, enabling more precise control over interconnect dimensions and electrical characteristics, thereby improving device performance consistency.
Data Source
Figure 1A~1B
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AI summary
One or more electrical interconnects are formed beneath a device region within a volume of semiconductor material in which electronic devices are formed. The buried interconnects extended in a lateral direction parallel to surfaces of the die toward an edge of the semiconductor die. Such buried interconnects can be exposed at edges of the die to provide electrical contacts along those edges and can be coupled to electronic devices formed within the device region as alternatives to or in addition to contacts formed on top or bottom surfaces of the die.