Buried Interconnection Line in Semiconductor Devices
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices necessitates improved integration and electrical characteristics, particularly in FinFET structures where traditional planar metal oxide semiconductor FETs face limitations due to reduced size.
Innovation Solution
A semiconductor device design featuring a buried interconnection line with a metal and semiconductor layer stack, surrounded by channel layers and a gate electrode, includes a buried insulating layer and source/drain regions, enhancing integration and electrical performance by reducing resistance and improving signal application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration is increased to meet high-performance demands, then device functionality and speed are improved, but manufacturing complexity and pattern precision requirements increase
Solution Approach 1:
The patent transitions from planar MOSFET to FinFET three-dimensional structure, adding vertical dimension to the channel. The gate electrode wraps around the channel in a FinFET configuration, providing better gate control and enabling higher integration density without proportionally increasing manufacturing precision requirements.
Solution Approach 2:
The patent implements nested interconnection structures where buried interconnection lines are embedded within the substrate, and multiple interconnection layers are stacked vertically. Contact plugs and vias are nested within insulating layers to connect different interconnection levels, enabling high-density integration.
2Productivity
If planar MOSFET size is reduced to increase integration, then device density is improved, but electrical characteristics deteriorate
Solution Approach 1:
The patent employs FinFET three-dimensional structure where the channel is formed as a vertical fin with gate electrode wrapping around it. This provides superior gate control over the channel compared to planar MOSFET, maintaining excellent electrical characteristics even at reduced device dimensions and enabling continued scaling.
Solution Approach 2:
The patent uses composite material structures including semiconductor layers with different compositions (e.g., SiGe source/drain regions with silicon channel), high-k dielectric materials for gate insulation, and metal combinations for interconnection lines. These composite structures optimize electrical characteristics while enabling high-density integration.
3Reliability
If buried interconnection line structure is implemented, then resistance is reduced and signal delivery is enhanced, but device structure complexity increases
Solution Approach 1:
The patent divides the interconnection system into multiple segments: buried interconnection lines embedded in the substrate, intermediate contact plugs, upper interconnection layers, and via connections. Each segment is optimized independently and connected through standardized interfaces, managing complexity through modular design.
Solution Approach 2:
The patent combines the buried interconnection line function with the substrate structure itself, embedding conductive lines within the semiconductor substrate during fabrication. This merging of interconnection functionality with the substrate reduces the number of separate components and simplifies the overall device structure.
Data Source
AI summary
A semiconductor device includes a buried interconnection line extending in a first direction, a gate electrode extending in a second direction intersecting the buried interconnection line, and channel layers spaced apart from each other in a third direction perpendicular to the first direction and the second direction. The channel layers are surrounded by the gate electrode, and the buried interconnection line includes a metal layer and a semiconductor layer stacked in the third direction. The device includes a buried insulating layer between the channel layers and the buried interconnection line, and first and second source/drain regions in contact with the channel layers on both sides of the gate electrode. The second source/drain region penetrates through the buried insulating layer and is in contact with the semiconductor layer. The device includes a contact plug on the first source/drain region, and a via below the buried interconnection line.