Buried Layer Layout in Semiconductor FETs for Leakage Control
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Solution Overview
Problem
Semiconductor devices face challenges in achieving high reliability and integration with advanced electronic industry demands for high speed and multi-functionality, particularly in the fabrication of field effect transistors where existing technologies struggle to optimize performance and reduce leakage currents.
Innovation Solution
A semiconductor device design featuring a substrate with active patterns, gate electrodes, source/drain patterns, and a buried layer with varying levels to enhance channel and source/drain regions, along with gate spacers and dielectric layers, which improves device isolation and reduces parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional buried layer structure is used, then fabrication is simpler, but leakage currents increase and reliability decreases
Solution Approach 1:
The buried layer is segmented into multiple regions with different depth levels: a first buried layer region at a first depth level and a second buried layer region at a second depth level. This segmentation allows different portions of the buried layer to serve different functions - reducing leakage currents in one region while managing parasitic capacitance in another, thereby improving overall device reliability without requiring complete structural redesign
Solution Approach 2:
Different depth levels are assigned to different regions of the buried layer based on local requirements. The first buried layer region extends to a greater depth than the second buried layer region, creating localized variations in electrical properties. This local quality approach optimizes leakage current reduction in specific areas while maintaining appropriate parasitic capacitance characteristics in other areas
2Reliability
If the buried layer depth is increased to reduce leakage currents, then reliability improves, but parasitic capacitance increases
Solution Approach 1:
The buried layer is divided into depth segments where the first buried layer region extends to a first depth level and the second buried layer region extends to a second depth level. This segmentation enables the structure to reduce leakage currents through deeper extension in the first region while limiting parasitic capacitance increase by restricting the second region's depth, thus balancing both competing requirements
Solution Approach 2:
Different depth levels are assigned to different buried layer regions based on local electrical requirements. The first buried layer region has greater depth for optimal leakage current reduction, while the second buried layer region has controlled depth to manage parasitic capacitance, creating localized electrical properties that optimize overall device performance
3Productivity
If device integration is increased to meet industry demands, then productivity and functionality improve, but fabrication precision requirements increase
Solution Approach 1:
The gate spacers are formed prior to the final active pattern formation process. This preliminary action establishes reference structures that guide subsequent patterning steps, ensuring that active patterns are formed with correct alignment and dimensions. By preparing the gate spacers in advance, the fabrication process achieves higher precision in integrated device structures without requiring complex real-time adjustments
Data Source
AI summary
Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a substrate provided with an active pattern, a gate electrode that runs across the active pattern and extends in a first direction, source/drain patterns on the active pattern on opposite sides of the gate electrode, a channel pattern formed of a portion of the active pattern between the source/drain patterns, and a buried layer below the source/drain patterns and the channel pattern. The buried layer includes first segments below the source/drain patterns and a second segment below the channel pattern. The first segments have a first level. The second segment has a second level. The first level is lower than the second level.