Buried Layer Overlap for High-Voltage Semiconductor Breakdown
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Solution Overview
Problem
Existing high-voltage semiconductor devices face challenges in achieving high breakdown voltage and reducing leakage current due to close doping profiles between well regions, leading to device failure under varying voltages.
Innovation Solution
Incorporating a buried layer with a specific conductivity type in the semiconductor substrate, overlapping with well regions, which widens the distance between doping profiles and reduces charge punching, thereby enhancing breakdown voltage and preventing device failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If well regions are placed close together to reduce device area, then device integration density is improved, but breakdown voltage decreases and leakage current increases due to overlapping doping profiles
Solution Approach 1:
An intrinsic or lightly-doped semiconductor layer is introduced between the first and second well regions to act as an intermediary barrier. This intermediate layer prevents direct interaction between the heavily-doped well regions, blocking charge carrier punching through while allowing the wells to remain in close proximity for high integration density.
Solution Approach 2:
The problem of vertical doping profile overlap is solved by transitioning to a lateral separation approach. The well regions are positioned adjacent to each other in the horizontal plane rather than being stacked vertically, with the intrinsic layer providing lateral isolation between the doped regions.
2Area of stationary object
If well regions are placed close together to reduce device area, then device integration density is improved, but leakage current increases due to overlapping doping profiles
Solution Approach 1:
The intrinsic or lightly-doped semiconductor layer serves as a mediating barrier between the well regions, intercepting and blocking the flow of leakage current that would otherwise occur through direct doping profile overlap. This intermediate layer acts as a purification zone that eliminates the harmful interaction between adjacent wells.
3Reliability
If doping profiles are kept separate to maintain breakdown voltage, then reliability is improved, but device area increases due to larger spacing between well regions
Solution Approach 1:
The patent transitions from vertical stacking of well regions to lateral adjacency arrangement. By placing wells side-by-side in the horizontal plane rather than one above the other, the design achieves both electrical isolation (maintaining breakdown voltage) and space efficiency (reducing overall device area).
Solution Approach 2:
The intrinsic or lightly-doped layer is strategically positioned only in the critical regions between well regions where charge punching occurs, rather than uniformly throughout the entire device. This localized approach maintains high doping concentrations in the wells for good conductivity while providing isolation only where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The buried layer significantly increases breakdown voltage from approximately 4V to 98V, reduces leakage current, and maintains threshold voltage, ensuring device reliability under different voltage applications.
Implementation Method 1
the buried layer is overlapped with the first well region and the second well region, and the buried layer is directly below the first source region... the buried layer significantly increases breakdown voltage from approximately 4V to 98V, reduces leakage current
Data Source
AI summary
A high-voltage semiconductor device includes a semiconductor substrate having a first conductivity type. A first well region is disposed on the semiconductor substrate and has the first conductivity type. A second well region is adjacent to the first well region and has a second conductivity type opposite to the first conductivity type. A first source region and a first drain region is respectively disposed in the first well region and the second well region, wherein the first source region and the first drain region has the second conductivity type. A first gate structure is disposed on the first well region and the second well region, and a buried layer is disposed in the semiconductor substrate and has the first conductivity type, wherein the buried layer is overlapped with the first well region and the second well region, and the buried layer is directly below the first source region.