Buried Conductive Layer Spacer Layout for Gate-Induced Drain Leakage
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability due to issues such as gate-induced drain leakage, which is not effectively addressed by existing technologies.
Innovation Solution
The design incorporates an in-recess spacer in the semiconductor device, which reduces the electrical field near the buried conductive layer, thereby minimizing gate-induced drain leakage by ensuring the top and bottom surfaces of the spacer and conductive layers are coplanar, and the sidewalls are aligned, facilitating improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the dimensions of semiconductor devices are scaled down to meet increasing computing demand, then computing ability is improved, but gate-induced drain leakage increases and quality/yield/performance deteriorate
Solution Approach 1:
An in-recess spacer structure is introduced as an intermediary element between the buried conductive layer and the overlying structures. This spacer acts as a mediator that reduces the electrical field strength in the critical region, thereby suppressing gate-induced drain leakage while maintaining device scaling benefits. The spacer material and its recessed configuration provide a controlled transition zone that mitigates the harmful electrical field concentration.
2Ease of manufacture
If conventional structures are used without in-recess spacers, then manufacturing is simpler, but electrical field concentration causes increased gate-induced drain leakage
Solution Approach 1:
The structure is segmented by introducing a distinct in-recess spacer component that separates and isolates the buried conductive layer from adjacent structures. This segmentation creates a physical and electrical field barrier, dividing the continuous electrical field into controlled regions with reduced field strength at critical interfaces, thereby reducing gate-induced drain leakage.
Solution Approach 2:
The spacer is configured in a recessed dimension, extending vertically into the substrate rather than merely laterally. This dimensional approach creates a three-dimensional electrical field management structure that effectively reduces field concentration in the horizontal plane, addressing the leakage problem through vertical field distribution control.
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a buried conductive layer including a bottom portion positioned in the substrate, and a top portion positioned in the substrate and positioned on the bottom portion; and an in-recess spacer positioned in the substrate, surrounding the bottom portion, and covered by the top portion. A top surface of the top portion and a top surface of the substrate are substantially coplanar. A bottom surface of the in-recess spacer and a bottom surface of the bottom portion are substantially coplanar. A sidewall of the in-recess spacer and a sidewall of the top portion are substantially coplanar.