Buried Local Interconnect Layout for Scalable CFET CMOS Cells
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Solution Overview
Problem
The scalability of complementary field-effect transistor (CFET) technology is limited by design congestion and the need for additional space to accommodate interconnects, which complicates the interconnection of stacked transistors and CMOS cells, leading to reliability issues and increased complexity.
Innovation Solution
A buried local interconnect is introduced that establishes functional connections between CMOS cells without extending above the top FET layer, reducing design congestion and minimizing height, thereby avoiding interference with other interconnects and simplifying the connection process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional interconnects are used to connect stacked transistors, then functional connections are established, but design congestion increases and additional space is required
Solution Approach 1:
The patent transitions from planar interconnects to three-dimensional buried local interconnects that extend vertically between stacked transistor layers. This dimensional change allows interconnects to pass through isolation regions between transistor stacks, enabling connections without increasing lateral design congestion while maintaining functional reliability.
2Ease of operation
If interconnects extend above the top FET layer, then connections are established, but interference with other interconnects occurs
Solution Approach 1:
The patent extracts the interconnect function from the lateral plane and relocates it to the vertical dimension within isolation regions. By taking out the interconnect path from the congested lateral space and placing it in the vertical dimension through isolation regions, the solution eliminates interference with other interconnects while preserving connection capability.
3Productivity
If stacked transistor configurations are used, then device density increases, but interconnection complexity increases
Solution Approach 1:
The patent implements nested interconnect structures where buried local interconnects are embedded within isolation regions that are themselves part of the stacked transistor architecture. This nesting allows multiple interconnect levels to be integrated vertically without increasing lateral complexity, maintaining high device density while simplifying interconnection routing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces design complexity, enhances scalability, and prevents interference with other interconnects, allowing for more efficient and reliable interconnection of stacked transistors and CMOS cells, thus improving the overall performance and reliability of CFET technology.
Implementation Method 1
forming a first layer including a first area of epitaxy material and a second area of epitaxy material. The first layer has a first polarity. The integrated circuit component further includes a second layer including a third area of epitaxy material and a fourth area of epitaxy material. The second layer has a second polarity that is different than the first polarity.
Data Source
AI summary
An integrated circuit component includes a first layer including first and second areas of epitaxy material. The first layer has a first polarity. The component further includes a second layer including third and fourth areas of epitaxy material. The second layer has a second polarity that is different than the first polarity. The third area is arranged at least partially above the first area, and the fourth area is arranged at least partially above the second area. The integrated circuit component further includes an interconnect in direct contact with one of the first area and the third area and in direct contact with one of the second area and the fourth area. The interconnect has a top surface that does not extend substantially above an uppermost surface of the second layer.