Buried Local Interconnect in Source/Drain Regions
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Solution Overview
Problem
The scaling of semiconductor devices is limited by the area required for routing cross-coupling structures in memory cells, such as SRAMs, which affects the performance and durability of memory devices.
Innovation Solution
A method for forming buried local interconnects in source/drain regions, involving the creation of vertically oriented channel structures, forming source/drain regions, isolation structures, and trenches, followed by the deposition of conductive lines and dielectric materials to reduce the device footprint while maintaining effective charge storage and signal inversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional routing structures are used for cross-coupling in memory cells, then the device can maintain simple manufacturing processes, but the device footprint area increases
Solution Approach 1:
The patent transitions from planar routing to three-dimensional routing by forming conductive lines within trenches etched into the source/drain regions themselves. This vertical integration into the substrate depth allows interconnects to pass through the source/drain regions rather than routing around them in the planar layer, effectively utilizing the third dimension (depth) to reduce surface footprint while managing routing complexity through structured trench formation.
Solution Approach 2:
The conductive interconnect lines are nested within the source/drain region trenches, embedding the routing structure inside the existing device geometry. This nesting approach allows the interconnects to occupy space within the source/drain regions rather than requiring additional lateral space, thereby reducing the overall device footprint while maintaining manufacturing feasibility through integrated process steps.
2Productivity
If the device footprint is reduced through scaling, then productivity and memory device density improve, but the area for routing cross-coupling structures becomes insufficient
Solution Approach 1:
By routing conductive lines through trenches in the source/drain regions, the patent exploits the vertical dimension to create interconnect paths that do not consume additional lateral routing area. This allows memory device density to increase through footprint reduction while the routing function is maintained through depth utilization rather than lateral expansion.
Solution Approach 2:
The source/drain regions serve dual functions: they provide the standard transistor source/drain functionality while simultaneously housing the interconnect routing structures within their trenches. This multi-functionality eliminates the need for separate dedicated routing areas, enabling density improvement without sacrificing routing capability.
3Area of stationary object
If buried local interconnects are formed in source/drain regions, then the device footprint is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct sequential steps: forming the source/drain regions, etching trenches within them, depositing conductive material, and planarizing. This segmentation of the complex buried interconnect formation into manageable process modules makes the increased manufacturing complexity tractable through standardized, repeatable fabrication steps rather than a monolithic difficult process.
Solution Approach 2:
The source/drain regions are formed first with their trenches prepared in advance before the conductive interconnect material is deposited. This preliminary preparation of the routing pathways ensures that subsequent manufacturing steps can proceed efficiently with the interconnects being placed into pre-defined locations, reducing the overall manufacturing complexity compared to attempting to form both structures simultaneously or in reverse sequence.
Data Source
AI summary
A method for forming a buried local interconnect in a source/drain region is disclosed including, among other things, forming a plurality of VOC structures, forming a first source/drain region between a first pair of the plurality of VOC structures, forming a second source/drain region between a second pair of the plurality of VOC structures, and forming an isolation structure between the first and second source/drain regions. A first trench is formed in the first and second source/drain regions and the isolation structure. A liner layer is formed in the first trench, and a first conductive line is formed in the first trench. A dielectric material is formed above the first conductive line. A first opening is formed in the dielectric material to expose a portion of the first conductive line. A first conductive feature is formed in the first opening contacting the exposed portion of the first conductive line.