Buried Connection Lines in Logic Cells to Ease Routing Congestion
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Solution Overview
Problem
Conventional memory devices face challenges in reducing the size of logic cells without decreasing the number of routing tracks, which leads to increased congestion and reduced array efficiency as memory cell arrays become denser and smaller.
Innovation Solution
The implementation of buried connection lines within the trench isolation region of logic cells allows for maintaining or increasing the number of routing tracks while decreasing the logic cell area, thereby preserving array efficiency without additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number of predetermined tracks in each standard cell is increased to provide more routing options, then routing congestion is relaxed, but the cell area increases due to minimum pitch requirements
Solution Approach 1:
The patent utilizes the vertical dimension by embedding connection lines within the trench isolation region beneath the active transistor area. This allows routing tracks to be added without increasing the horizontal cell footprint, as connections are established in the third dimension (depth) rather than expanding the planar grid.
Solution Approach 2:
The connection lines are nested within the trench isolation structure, which itself is embedded in the semiconductor substrate. This nested arrangement allows routing infrastructure to be contained within existing structural elements without occupying additional cell area.
2Area of stationary object
If the memory cell array size is decreased to reduce memory device size, then device footprint is reduced, but the standard cell size must also be decreased which reduces the number of predetermined tracks for routing
Solution Approach 1:
By moving routing tracks into the vertical dimension (embedding in trench isolation), the patent decouples the relationship between cell area and number of tracks. Smaller cells can maintain adequate routing capacity because tracks are stacked vertically rather than requiring proportional horizontal space.
3Area of stationary object
If the standard cell height is decreased to reduce cell area, then cell footprint is reduced, but the number of predetermined tracks in the row direction must be reduced
Solution Approach 1:
The patent compensates for reduced vertical space by creating horizontal routing tracks within the trench isolation region. This allows row-direction tracks to be embedded laterally beneath the active area, maintaining track count despite reduced cell height.
4Area of stationary object
If the standard cell width is decreased to reduce cell area, then cell footprint is reduced, but the number of predetermined tracks in the column direction must be reduced
Solution Approach 1:
Column-direction tracks are embedded within the trench isolation region, allowing vertical routing to be maintained even when cell width is reduced. The trench structure provides a protected pathway for column tracks that does not depend on horizontal cell dimensions.
Data Source
AI summary
An apparatus includes a substrate and a memory cell array disposed on the substrate. The apparatus also includes a logic cell disposed on the substrate in a peripheral region adjacent the memory cell array. The apparatus further includes a trench isolation region disposed in the substrate in the peripheral region. The trench isolation region either separates a first active area of the logic cell from a second active area of the logic cell or separates the logic cell from an adjacent logic cell. The logic cell includes a connection line that is buried within the trench isolation region. The connection line can be formed as an extension of a buried word line in the memory cell array region during a same fabrication process that forms the corresponding buried word line. By extending the buried word line into the peripheral region, the buried connection line can be formed without additional processing.