Multilayer Buried MIM Capacitor Selective Etch
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Solution Overview
Problem
Conventional metal-insulator-metal (MIM) capacitors on bulk silicon substrates face challenges due to high manufacturing costs and limited horizontal area, which restricts their performance and scaling in densely built semiconductor integrated circuits.
Innovation Solution
A method involving a double selective etch process is used to form a semiconductor structure with alternating metal layers, eliminating the need for a hardmask and allowing for a denser structure with multiple metal layers, enabling efficient adjustment of capacitance and thermal stability by recessing one type of metal layer relative to the other within trenches, thereby forming high-capacity MIM capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional MIM capacitors are fabricated with offset metal layers requiring separate masking layers, then manufacturing precision can be maintained, but manufacturing cost increases and device complexity increases
Solution Approach 1:
The patent combines multiple metal layers (first conductive layers and second conductive layers) into a single integrated structure where they are formed simultaneously or in sequence without requiring separate masking operations for each layer. This merging of layers reduces the number of masking steps and lowers manufacturing complexity while maintaining the capacitor function.
Solution Approach 2:
The alternating first and second conductive layers serve multiple functions: they form the capacitor electrodes, provide electrical connections, and enable capacitance tuning through selective etching. This multi-functionality reduces the need for separate masking layers that would otherwise be required for each metal layer alignment.
2Quantity of substance
If more metal layers are added to increase capacitance, then capacitor capacity improves, but horizontal area consumption increases
Solution Approach 1:
The patent transitions from a planar capacitor design to a vertical stacked design with alternating conductive layers separated by dielectric layers. By stacking multiple capacitor units vertically, the design achieves high capacitance capacity while minimizing the horizontal footprint on the chip.
Solution Approach 2:
The structure nests multiple conductive layers and dielectric layers within each other in a vertical stack, similar to nested dolls. Each alternating layer pair forms a capacitor unit, and multiple units are nested vertically to achieve high total capacitance in a compact volume.
3Manufacturing precision
If selective etching is used to recess first conductive layers faster than second conductive layers, then manufacturing precision is improved for capacitor formation, but process complexity increases
Solution Approach 1:
The patent applies selective etching that targets specific first conductive layers with different etch rates compared to second conductive layers. This local differentiation in etch response allows precise control over which layers are recessed and by how much, enabling accurate capacitor electrode formation without requiring complex multi-step alignment processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, increases the number of metal layers, and enhances thermal stability, allowing for improved capacitance and performance without material degradation, addressing the limitations of conventional MIM capacitors.
Implementation Method 1
first etching the first trench selective to the plurality of alternating first conductive layers and second conductive layers, wherein the first conductive layers are etched faster than the second conductive layers
Data Source
AI summary
Metal-on-metal insulator structures and methods for making the same. The method includes: providing an insulator layer overlying a semiconductor substrate, forming a plurality of alternating first conductive layers and second conductive layers on the insulator layer, forming at least one dielectric layer between each of the alternating first conductive layers and second conductive layers, forming a first trench at a first location through a first portion of the plurality of the alternating first conductive layers and second conductive layers and the at least one dielectric layer, and first etching the first trench selective to the plurality of alternating first conductive layers and second conductive layers, wherein the first conductive layers are etched faster than the second conductive layers to form a first modified trench, wherein the first conductive layers are recessed relative to the center of the first modified trench greater than the second conductive layers.