Buried MIM Capacitor Layout for Stacked Nanosheet FETs
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Solution Overview
Problem
Current MIM capacitor fabrication methods are complex and hinder capacitance density increase and yield improvement due to high process overhead and parallel capacitance issues in semiconductor manufacturing.
Innovation Solution
A metal-insulator-metal (MIM) capacitor is integrated between adjacent stacked nanosheet field effect transistors, formed in a buried power rail trench, reducing parallel capacitance and improving capacitance density by optimizing the capacitor's placement and structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional stacking methods are used to fabricate MIM capacitors, then capacitor layers can be formed, but process complexity increases and manufacturing efficiency decreases
Solution Approach 1:
The patent combines the MIM capacitor fabrication process with the existing BEOL manufacturing process. The capacitor electrodes are formed using the same metal layer deposition and patterning steps as the interconnect structures, eliminating the need for separate capacitor-specific processing. This merging of processes reduces overall fabrication complexity while maintaining capacitance density improvements.
2Manufacturing precision
If multiple lithography and etching steps are used for MIM capacitor fabrication, then capacitor structure can be created, but manufacturing time and process overhead increase
Solution Approach 1:
The patent designs the MIM capacitor structure to be compatible with universal BEOL processing steps. The same lithography and etching processes used for creating interconnect patterns are also used to define capacitor electrodes and insulator regions. This multi-functionality approach allows a single set of processing steps to serve both interconnect and capacitor fabrication needs, reducing total manufacturing time while maintaining structural precision.
3Reliability
If extra processing steps are added for specific MIM capacitor designs, then capacitor performance can be optimized, but integration difficulty into conventional BEOL process increases
Solution Approach 1:
The patent segments the capacitor structure into distinct functional regions (electrodes, insulator layers, dielectric material) that can be formed using separate but compatible processing modules within the BEOL flow. This segmentation allows each region to be optimized for its specific function while being manufactured using standard process steps, facilitating easier integration into conventional BEOL manufacturing without requiring complex unified processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances AC performance, increases capacitance density, and reduces sensitivity to process defects, providing a more efficient and scalable solution for semiconductor manufacturing.
Implementation Method 1
Voltage is applied across the metal electrodes which results in charge storage within the formed capacitor configuration
Data Source
AI summary
A metal insulator metal capacitor (MIM capacitor) between adjacent stacked nanosheet FETs, each include a first nanosheet stack including alternating layers of a first work function metal and a semiconductor channel material vertically aligned and stacked one on top of another and a second nanosheet stack including alternating layers of a second work function metal and the semiconductor channel material vertically aligned and stacked one on top of another, the second nanosheet stack on the first nanosheet stack. Forming adjacent stacked nanosheet FETs, each include a first nanosheet stack and a second nanosheet stack, the second nanosheet stack on the first nanosheet stack, and forming a MIM capacitor between adjacent stacked nanosheet field effect transistors.